Editing intel/xeon gold/5218r

{{intel title|Xeon Gold 5218R}}
{{chip
|name=Xeon Gold 5218R
|image=cascade lake sp (front).png
|designer=Intel
|manufacturer=Intel
|model number=5218R
|market=Server
|first announced=February 24, 2020
|first launched=February 24, 2020
|release price (tray)=$1,273.00
|release price (box)=$1,280.00
|family=Xeon Gold
|series=6200
|locked=Yes
|frequency=2,100 MHz
|turbo frequency1=4,000 MHz
|bus type=DMI 3.0
|bus links=4
|bus rate=8 GT/s
|clock multiplier=21
|isa=x86-64
|isa family=x86
|microarch=Cascade Lake
|platform=Purley
|chipset=Lewisburg
|core name=Cascade Lake R
|core family=6
|core model=85
|process=14 nm
|technology=CMOS
|word size=64 bit
|core count=20
|thread count=40
|max memory=1 TiB
|max cpus=2
|smp interconnect=UPI
|smp interconnect links=2
|smp interconnect rate=10.4 GT/s
|tdp=125 W
|tcase min=0 °C
|tcase max=87 °C
|package name 1=intel,fclga_3647
|predecessor=Xeon Gold 5218
|predecessor link=intel/xeon_gold/5218
}}
'''Xeon Gold 5218R''' is a {{arch|64}} [[20-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2020]]. The Gold 5218R is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 2-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.1 GHz with a TDP of 125 W and features a {{intel|turbo boost}} frequency of up to 4.0 GHz.

== Cache ==
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
{{cache size
|l1 cache=1.25 MiB
|l1i cache=640 KiB
|l1i break=20x32 KiB
|l1i desc=8-way set associative
|l1d cache=640 KiB
|l1d break=20x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=20 MiB
|l2 break=20x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=27.5 MiB
|l3 break=20x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2666
|ecc=Yes
|max mem=1 TiB
|controllers=2
|channels=6
|max bandwidth=119.21 GiB/s
|bandwidth schan=19.87 GiB/s
|bandwidth dchan=39.74 GiB/s
|bandwidth qchan=79.47 GiB/s
|bandwidth hchan=119.21 GiB/s
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5218R - Intel#pcie +
base frequency	2,100 MHz (2.1 GHz, 2,100,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	21 +
core count	20 +
core family	6 +
core model	85 +
core name	Cascade Lake R +
designer	Intel +
family	Xeon Gold +
first announced	February 24, 2020 +
first launched	February 24, 2020 +
full page name	intel/xeon gold/5218r +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	640 KiB (655,360 B, 0.625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	640 KiB (655,360 B, 0.625 MiB) +
l2$ description	16-way set associative +
l2$ size	20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
l3$ description	11-way set associative +
l3$ size	27.5 MiB (28,160 KiB, 28,835,840 B, 0.0269 GiB) +
ldate	February 24, 2020 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	360.15 K (87 °C, 188.6 °F, 648.27 °R) +
max cpu count	2 +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	5218R +
name	Xeon Gold 5218R +
number of avx-512 execution units	1 +
package	FCLGA-3647 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,273.00 (€ 1,145.70, £ 1,031.13, ¥ 131,539.09) + and $ 1,280.00 (€ 1,152.00, £ 1,036.80, ¥ 132,262.40) +
release price (box)	$ 1,280.00 (€ 1,152.00, £ 1,036.80, ¥ 132,262.40) +
release price (tray)	$ 1,273.00 (€ 1,145.70, £ 1,031.13, ¥ 131,539.09) +
series	6200 +
smp interconnect	UPI +
smp interconnect links	2 +
smp interconnect rate	10.4 GT/s +
smp max ways	2 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2666 +
tdp	125 W (125,000 mW, 0.168 hp, 0.125 kW) +
technology	CMOS +
thread count	40 +
turbo frequency (1 core)	4,000 MHz (4 GHz, 4,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +