Editing intel/xeon gold/5220r

From WikiChip

Revision as of 21:45, 27 February 2020 by David (talk | contribs) (5220R)

(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)

Warning: You are editing an out-of-date revision of this page. If you save it, any changes made since this revision will be lost.

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Summary:

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

Templates used on this page:

Template:arch (view source) (protected)
Template:cache size (view source) (protected)
Template:chip (view source) (protected)
Template:expansions entry (edit)
Template:expansions main (edit)
Template:intel (view source) (protected)
Template:intel title (view source) (protected)
Template:istrue (view source) (protected)
Template:link-intel (view source) (protected)
Template:link-x86 (view source) (protected)
Template:main (view source) (protected)
Template:memory controller (edit)
Template:url parse anchor (view source) (protected)
Template:url parse article (view source) (protected)
Template:x86 (view source) (protected)
Template:x86 features (view source) (protected)
Module:chip (view source)
Module:expansions (view source)
Module:packaging data (view source)

Retrieved from "https://en.wikichip.org/wiki/intel/xeon_gold/5220r"

Facts about "Xeon Gold 5220R - Intel"

RDF feed

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5220R - Intel#pcie +
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	22 +
core count	24 +
core family	6 +
core model	85 +
core name	Cascade Lake R +
designer	Intel +
family	Xeon Gold +
first announced	February 24, 2020 +
first launched	February 24, 2020 +
full page name	intel/xeon gold/5220r +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	768 KiB (786,432 B, 0.75 MiB) +
l1i$ description	8-way set associative +
l1i$ size	768 KiB (786,432 B, 0.75 MiB) +
l2$ description	16-way set associative +
l2$ size	24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
l3$ description	11-way set associative +
l3$ size	35.75 MiB (36,608 KiB, 37,486,592 B, 0.0349 GiB) +
ldate	February 24, 2020 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	359.15 K (86 °C, 186.8 °F, 646.47 °R) +
max cpu count	2 +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	5220R +
name	Xeon Gold 5220R +
number of avx-512 execution units	2 +
package	FCLGA-3647 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,555.00 (€ 1,399.50, £ 1,259.55, ¥ 160,678.15) + and $ 1,561.00 (€ 1,404.90, £ 1,264.41, ¥ 161,298.13) +
release price (box)	$ 1,561.00 (€ 1,404.90, £ 1,264.41, ¥ 161,298.13) +
release price (tray)	$ 1,555.00 (€ 1,399.50, £ 1,259.55, ¥ 160,678.15) +
series	6200 +
smp interconnect	UPI +
smp interconnect links	2 +
smp interconnect rate	10.4 GT/s +
smp max ways	2 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2666 +
tdp	150 W (150,000 mW, 0.201 hp, 0.15 kW) +
technology	CMOS +
thread count	48 +
turbo frequency (1 core)	4,000 MHz (4 GHz, 4,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas

Samsung