Editing amd/epyc/7552

{{amd title|EPYC 7552}}
{{chip
|name=EPYC 7552
|no image=Yes
|designer=AMD
|manufacturer=TSMC
|manufacturer 2=GlobalFoundries
|model number=7552
|part number=100-000000076
|market=Server
|first announced=August 7, 2019
|first launched=August 7, 2019
|release price=$4025.00
|family=EPYC
|series=7002
|locked=Yes
|frequency=2,200 MHz
|turbo frequency=3,350 MHz
|clock multiplier=22
|isa=x86-64
|isa family=x86
|microarch=Zen 2
|core name=Rome
|core family=23
|process=7 nm
|process 2=14 nm
|technology=CMOS
|mcp=Yes
|die count=7
|word size=64 bit
|core count=48
|thread count=96
|max cpus=2
|max memory=4 TiB
|tdp=200 W
|package name 1=amd,socket_sp3
|predecessor=EPYC 7551
|predecessor link=amd/epyc/7551
}}
'''EPYC 7552''' is a {{arch|64}} [[48-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7552 has a TDP of 200 W with a base frequency of 2.2 GHz and a {{amd|precision boost|boost}} frequency of up to 3.35 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.

== Cache ==
{{main|amd/microarchitectures/zen 2#Memory_Hierarchy|l1=Zen 2 § Cache}}
{{cache size
|l1 cache=3 MiB
|l1i cache=1.5 MiB
|l1i break=48x32 KiB
|l1i desc=8-way set associative
|l1d cache=1.5 MiB
|l1d break=48x32 KiB
|l1d desc=8-way set associative
|l2 cache=24 MiB
|l2 break=48x512 KiB
|l2 desc=8-way set associative
|l2 policy=write-back
|l3 cache=192 MiB
|l3 break=12x16 MiB
}}

== Memory controller ==
{{memory controller
|type=DDR4-3200
|ecc=Yes
|max mem=4 TiB
|controllers=8
|channels=8
|max bandwidth=190.7 GiB/s
|bandwidth schan=23.84 GiB/s
|bandwidth dchan=47.68 GiB/s
|bandwidth qchan=95.37 GiB/s
|bandwidth hchan=143.1 GiB/s
|bandwidth ochan=190.7 GiB/s
}}

== Expansions ==
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=4.0
|pcie lanes=128
|pcie config=x16
|pcie config 2=x8
}}
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=Yes
|sse_gfni=No
|avx=Yes
|avx_gfni=No
|avx2=Yes
|avx512f=No
|avx512cd=No
|avx512er=No
|avx512pf=No
|avx512bw=No
|avx512dq=No
|avx512vl=No
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx512vnni=No
|avx5124vnniw=No
|avx512vpopcntdq=No
|avx512gfni=No
|avx512vaes=No
|avx512vbmi2=No
|avx512bitalg=No
|avx512vpclmulqdq=No
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=Yes
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|bfloat16=No
|tbt1=No
|tbt2=No
|tbmt3=No
|tvb=No
|bpt=No
|eist=No
|sst=No
|flex=No
|fastmem=No
|ivmd=No
|intelnodecontroller=No
|intelnode=No
|kpt=No
|ptt=No
|intelrunsure=No
|mbe=No
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=No
|txt=No
|ht=No
|vpro=No
|vtx=No
|vtd=No
|ept=No
|mpx=No
|sgx=No
|securekey=No
|osguard=No
|intqat=No
|dlboost=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=Yes
|amdv=Yes
|amdsme=Yes
|amdtsme=Yes
|amdsev=Yes
|rvi=No
|smt=Yes
|sensemi=Yes
|xfr=No
|xfr2=No
|mxfr=No
|amdpb=No
|amdpb2=Yes
|amdpbod=No
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	EPYC 7552 - AMD#pcie +
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
clock multiplier	22 +
core count	48 +
core family	23 +
core model	49 +
core name	Rome +
core stepping	B0 +
designer	AMD +
die count	7 +
family	EPYC +
first announced	August 7, 2019 +
first launched	August 7, 2019 +
full page name	amd/epyc/7552 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd precision boost 2	true +
has amd secure encrypted virtualization technology	true +
has amd secure memory encryption technology	true +
has amd sensemi technology	true +
has amd transparent secure memory encryption technology	true +
has ecc memory support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Precision Boost 2 +
has locked clock multiplier	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	3,072 KiB (3,145,728 B, 3 MiB) +
l1d$ description	8-way set associative +
l1d$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l1i$ description	8-way set associative +
l1i$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l2$ description	8-way set associative +
l2$ size	24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
l3$ size	192 MiB (196,608 KiB, 201,326,592 B, 0.188 GiB) +
ldate	August 7, 2019 +
manufacturer	TSMC + and GlobalFoundries +
market segment	Server +
max cpu count	2 +
max memory	4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
max memory bandwidth	190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels	8 +
microarchitecture	Zen 2 +
model number	7552 +
name	EPYC 7552 +
package	FCLGA-4094 + and SP3 +
part number	100-000000076 + and 100-100000076WOF +
process	7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 4,025.00 (€ 3,622.50, £ 3,260.25, ¥ 415,903.25) +
series	7002 +
smp max ways	2 +
socket	LGA-4094 + and SP3 +
supported memory type	DDR4-3200 +
tdp	200 W (200,000 mW, 0.268 hp, 0.2 kW) +
technology	CMOS +
thread count	96 +
turbo frequency	3,350 MHz (3.35 GHz, 3,350,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +