Editing amd/epyc/7502p

{{amd title|EPYC 7502P}}
{{chip
|name=EPYC 7502P
|no image=Yes
|designer=AMD
|manufacturer=TSMC
|manufacturer 2=GlobalFoundries
|model number=7502P
|part number=100-000000045
|market=Server
|first announced=August 7, 2019
|first launched=August 7, 2019
|family=EPYC
|series=7002
|locked=Yes
|frequency=2,500 MHz
|turbo frequency=3,350 MHz
|clock multiplier=25
|isa=x86-64
|isa family=x86
|microarch=Zen 2
|core name=Rome
|core family=23
|process=7 nm
|process 2=14 nm
|technology=CMOS
|mcp=Yes
|die count=5
|word size=64 bit
|core count=32
|thread count=64
|max cpus=1
|max memory=4 TiB
|tdp=180 W
|package name 1=amd,socket_sp3
}}
'''EPYC 7502P''' is a {{arch|64}} [[dotriaconta-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7502P has a TDP of 180 W with a base frequency of 2.5 GHz and a {{amd|precision boost|boost}} frequency of up to 3.35 GHz. This processor supports single-socket configurations only and up to 4 TiB of eight channels DDR4-3200 memory per socket.

== Cache ==
{{main|amd/microarchitectures/zen 2#Memory_Hierarchy|l1=Zen 2 § Cache}}
{{cache size
|l1 cache=2 MiB
|l1i cache=1 MiB
|l1i break=32x32 KiB
|l1i desc=8-way set associative
|l1d cache=1 MiB
|l1d break=32x32 KiB
|l1d desc=8-way set associative
|l2 cache=16 MiB
|l2 break=32x512 KiB
|l2 desc=8-way set associative
|l2 policy=write-back
|l3 cache=128 MiB
|l3 break=8x16 MiB
}}

== Memory controller ==
{{memory controller
|type=DDR4-3200
|ecc=Yes
|max mem=4 TiB
|controllers=8
|channels=8
|max bandwidth=190.7 GiB/s
|bandwidth schan=23.84 GiB/s
|bandwidth dchan=47.68 GiB/s
|bandwidth qchan=95.37 GiB/s
|bandwidth hchan=143.1 GiB/s
|bandwidth ochan=190.7 GiB/s
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	EPYC 7502P - AMD#pcie +
base frequency	2,500 MHz (2.5 GHz, 2,500,000 kHz) +
clock multiplier	25 +
core count	32 +
core family	23 +
core model	49 +
core name	Rome +
core stepping	B0 +
designer	AMD +
die count	5 +
family	EPYC +
first announced	August 7, 2019 +
first launched	August 7, 2019 +
full page name	amd/epyc/7502p +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd precision boost 2	true +
has amd secure encrypted virtualization technology	true +
has amd secure memory encryption technology	true +
has amd sensemi technology	true +
has amd transparent secure memory encryption technology	true +
has ecc memory support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Precision Boost 2 + and SenseMI Technology +
has locked clock multiplier	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	2,048 KiB (2,097,152 B, 2 MiB) +
l1d$ description	8-way set associative +
l1d$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ description	8-way set associative +
l1i$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l2$ description	8-way set associative +
l2$ size	16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
l3$ size	128 MiB (131,072 KiB, 134,217,728 B, 0.125 GiB) +
ldate	August 7, 2019 +
manufacturer	GlobalFoundries + and TSMC +
market segment	Server +
max cpu count	1 +
max memory	4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
max memory bandwidth	190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels	8 +
microarchitecture	Zen 2 +
model number	7502P +
name	EPYC 7502P +
package	FCLGA-4094 + and SP3 +
part number	100-000000045 + and 100-100000045WOF +
process	7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 2,300.00 (€ 2,070.00, £ 1,863.00, ¥ 237,659.00) +
series	7002 +
smp max ways	1 +
socket	LGA-4094 + and SP3 +
supported memory type	DDR4-3200 +
tdp	180 W (180,000 mW, 0.241 hp, 0.18 kW) +
technology	CMOS +
thread count	64 +
turbo frequency	3,350 MHz (3.35 GHz, 3,350,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +