Editing amd/epyc/7552

{{amd title|EPYC 7552}}
{{chip}}
'''EPYC 7552''' is a {{arch|64}} [[48-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7552 has a TDP of 200 W with a base frequency of 2.2 GHz and a {{amd|precision boost|boost}} frequency of up to 3.35 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	EPYC 7552 - AMD#pcie +
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
clock multiplier	22 +
core count	48 +
core family	23 +
core model	49 +
core name	Rome +
core stepping	B0 +
designer	AMD +
die count	7 +
family	EPYC +
first announced	August 7, 2019 +
first launched	August 7, 2019 +
full page name	amd/epyc/7552 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd precision boost 2	true +
has amd secure encrypted virtualization technology	true +
has amd secure memory encryption technology	true +
has amd sensemi technology	true +
has amd transparent secure memory encryption technology	true +
has ecc memory support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Precision Boost 2 +
has locked clock multiplier	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	3,072 KiB (3,145,728 B, 3 MiB) +
l1d$ description	8-way set associative +
l1d$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l1i$ description	8-way set associative +
l1i$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l2$ description	8-way set associative +
l2$ size	24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
l3$ size	192 MiB (196,608 KiB, 201,326,592 B, 0.188 GiB) +
ldate	August 7, 2019 +
manufacturer	TSMC + and GlobalFoundries +
market segment	Server +
max cpu count	2 +
max memory	4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
max memory bandwidth	190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels	8 +
microarchitecture	Zen 2 +
model number	7552 +
name	EPYC 7552 +
package	FCLGA-4094 + and SP3 +
part number	100-000000076 + and 100-100000076WOF +
process	7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 4,025.00 (€ 3,622.50, £ 3,260.25, ¥ 415,903.25) +
series	7002 +
smp max ways	2 +
socket	LGA-4094 + and SP3 +
supported memory type	DDR4-3200 +
tdp	200 W (200,000 mW, 0.268 hp, 0.2 kW) +
technology	CMOS +
thread count	96 +
turbo frequency	3,350 MHz (3.35 GHz, 3,350,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +