Editing intel/cores/ice lake u

{{intel title|Ice Lake U|core}}
{{core
|name=Ice Lake U
|image=ice lake u (front).png
|caption=Ice Lake U, front package
|back image=File:ice lake u (back).png
|developer=Intel
|manufacturer=Intel
|first announced=December, 2018
|first launched=May 27, 2019
|fate=Delayed
|isa=x86-64
|isa family=x86
|microarch=Ice Lake
|platform=Ice Lake
|word=64 bit
|proc=10 nm
|tech=CMOS
|package name 1=intel,fcbga_1526
|predecessor=Whiskey Lake U
|predecessor link=intel/cores/whiskey lake u
|predecessor 2=Cannon Lake U
|predecessor 2 link=intel/cores/cannon lake u
|successor=Tiger Lake U
|successor link=intel/cores/tiger lake u
|contemporary=Comet Lake U
|contemporary link=intel/cores/comet lake u
}}
'''Ice Lake U''' ('''ICL-U''') is the code name for [[Intel]]'s line of low-power mobile processors based on the {{intel|Ice Lake|l=arch}} microarchitecture, succeeding both {{\\|Cannon Lake U}} and {{\\|Whiskey Lake U}}. These chips are primarily targeted towards mainstream through premium tablets, thin-and-light, and other performance mobile devices. Ice Lake U processors are fabricated on Intel's enhanced [[10 nm process|10nm+ process]] and provide {{intel|ice_lake_(client)#Key_changes_from_Cannon_Lake.2FSkylake|significant amount of enhancements}} over the prior generation.


== Overview ==
Ice Lake U based processors are a single-chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All Ice Lake U processors use {{intel|FCBGA-1526}} packages.

=== Common Features ===
All Whiskey Lake U processors have the following:

* Quad/dual-channel Memory
** Up to dual-channel (2x64b) DDR4-3200
** Up to quad-channel (4x32b) LPDDR4X-3733
** 64 GiB
* 4x Thunderbolt 3 (USB 3.2 Gen 2x1 (10 Gb/s), Thunderbolt 3, DisplayPort 1.4)
* [[Quad-core]] with 8 threads (2 cores for lowest-end model)
* Everything up to AVX512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX1, AVX2, AVX512)
* {{intel|Turbo Boost}}, {{intel|Hyper-Threading}}, {{intel|Software Guard}}, {{intel|SpeedStep}}, {{intel|Speed Shift}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|OS Guard}}, {{intel|Flex Memory}}, {{intel|My WiFi Technology}}, and {{intel|Identity Protection Technology}}
* Support [[AHCI]], [[High Definition Audio]], 6x [[USB 3.2]] ports, 10x [[USB 2.0]] ports, 3x [[SATA III]]
* Graphics
** {{intel|Iris Plus Graphics}},{{intel|UHD Graphics}} ({{intel|Gen11|l=arch}} GT2)
** 3 independent displays supported
** Base frequency of 300 MHz
** Burst frequency of 0.9-1.15 GHz

{{clear}}

== Ice Lake U Processors ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc5 tc6">
{{comp table header|main|12:List of Ice Lake U Processors}}
{{comp table header|main|9:Main processor|3:Integrated Graphics}}
{{comp table header|cols|Price|Launched|Family|Cores|Threads|L3$|%TDP|%Frequency|%Turbo|Name|%Frequency|%Turbo}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Ice Lake U]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?microprocessor family
 |?core count
 |?thread count
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |format=template
 |template=proc table 3
 |userparam=14
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Ice Lake U]]}}
</table>
{{comp table end}}

=== SKU Comparison ===
Below are a number of SKU comparison graphs based on their specifications.

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by intel]] [[core name::Ice Lake U]]
 |?core count
 |?base frequency
 |charttitle=Cores vs. Base Frequency
 |numbersaxislabel=Frequency (MHz)
 |labelaxislabel=Core Count
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by intel]] [[core name::Ice Lake U]]
 |?core count
 |?turbo frequency (1 core)
 |charttitle=Cores vs. Turbo Frequency
 |numbersaxislabel=Frequency (MHz)
 |labelaxislabel=Core Count
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by intel]] [[core name::Ice Lake U]]
 |?core count
 |?tdp
 |charttitle=Cores vs. TDP
 |numbersaxislabel=TDP (W)
 |labelaxislabel=Core Count
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by intel]] [[core name::Ice Lake U]]
 |?turbo frequency (1 core)
 |?tdp
 |charttitle=Frequency vs. TDP
 |numbersaxislabel=TDP (W)
 |labelaxislabel=Frequency (MHz)
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

{{clear}}

== See also ==
{{intel ice lake core see also}}
back image	+
designer	Intel +
first announced	December 2018 +
first launched	May 27, 2019 +
instance of	core +
isa	x86-64 +
isa family	x86 +
main image	+
main image caption	Ice Lake U, front package +
manufacturer	Intel +
microarchitecture	Ice Lake +
name	Ice Lake U +
package	FCBGA-1526 +
platform	Ice Lake +
process	10 nm (0.01 μm, 1.0e-5 mm) +
socket	Type 4 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +