Editing intel/xeon w/w-3245m

{{intel title|Xeon W-3245M}}
{{chip
|name=Xeon W-3245M
|no image=Yes
|designer=Intel
|manufacturer=Intel
|model number=W-3245M
|part number=CD8069504248501
|s-spec=SRFFH
|market=Workstation
|release price (tray)=$5,002.00
|family=Xeon W
|series=W-3200
|locked=Yes
|frequency=3,200 MHz
|turbo frequency1=4,400 MHz
|bus type=DMI 3.0
|bus links=4
|bus rate=8 GT/s
|clock multiplier=32
|isa=x86-64
|isa family=x86
|microarch=Cascade Lake
|core name=Cascade Lake W
|core stepping=B1
|process=14 nm
|technology=CMOS
|word size=64 bit
|core count=16
|thread count=32
|max cpus=1
|max memory=1 TiB
|tdp=205 W
|package name 1=intel,fclga_3647
}}
'''W-3245M''' is a {{arch|64}} [[hexadeca-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture, operates at 3.2 GHz with a [[TDP]] of 205 W and a {{intel|turbo boost}} frequency of up to ? GHz.


{{unknown features}}


== Cache ==
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
{{cache size
|l1 cache=1 MiB
|l1i cache=512 KiB
|l1i break=16x32 KiB
|l1i desc=8-way set associative
|l1d cache=512 KiB
|l1d break=16x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=16 MiB
|l2 break=16x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=22 MiB
|l3 break=16x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2933
|ecc=Yes
|max mem=1.5 TiB
|controllers=2
|channels=6
|max bandwidth=131.13 GiB/s
|bandwidth schan=21.86 GiB/s
|bandwidth dchan=43.71 GiB/s
|bandwidth qchan=87.42 GiB/s
|bandwidth hchan=131.13 GiB/s
}}

== Expansions ==
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=48
|pcie config=x16
|pcie config 2=x8
|pcie config 3=x4
|pcie config 4=x1
}}
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=No
|avx=Yes
|avx2=Yes
|avx512f=Yes
|avx512cd=Yes
|avx512er=No
|avx512pf=No
|avx512bw=Yes
|avx512dq=Yes
|avx512vl=Yes
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx5124vnniw=No
|avx512vpopcntdq=No
|avx512units=2
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=No
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|tbt1=No
|tbt2=Yes
|tbmt3=No
|bpt=No
|eist=Yes
|sst=Yes
|flex=No
|fastmem=No
|ivmd=Yes
|intelnodecontroller=No
|intelnode=No
|kpt=No
|ptt=No
|intelrunsure=No
|mbe=No
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=Yes
|tsx=Yes
|txt=Yes
|ht=Yes
|vpro=Yes
|vtx=Yes
|vtd=Yes
|ept=Yes
|mpx=Yes
|sgx=No
|securekey=Yes
|osguard=Yes
|intqat=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=No
|amdv=No
|amdsme=No
|amdtsme=No
|amdsev=No
|rvi=No
|smt=No
|sensemi=No
|xfr=No
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon W-3245M - Intel#pcie +
base frequency	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
clock multiplier	32 +
core count	16 +
core name	Cascade Lake SP +
core stepping	B1 +
designer	Intel +
family	Xeon W +
first announced	June 3, 2019 +
first launched	June 3, 2019 +
full page name	intel/xeon w/w-3245m +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard +, Identity Protection Technology +, Turbo Boost Max Technology 3.0 + and Deep Learning Boost +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel identity protection technology support	true +
has intel secure key technology	true +
has intel speed shift technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost max technology 3 0	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
intel turbo boost max technology 3 0 frequency	4,600 MHz (4.6 GHz, 4,600,000 kHz) +
isa	x86-64 +
isa family	x86 +
l1$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l1d$ description	8-way set associative +
l1d$ size	512 KiB (524,288 B, 0.5 MiB) +
l1i$ description	8-way set associative +
l1i$ size	512 KiB (524,288 B, 0.5 MiB) +
l2$ description	16-way set associative +
l2$ size	16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
l3$ description	11-way set associative +
l3$ size	22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) +
ldate	June 3, 2019 +
main image	+
manufacturer	Intel +
market segment	Workstation +
max cpu count	1 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth	131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
model number	W-3245M +
name	Xeon W-3245M +
number of avx-512 execution units	2 +
package	FCLGA-3647 +
part number	CD8069504248501 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 5,002.00 (€ 4,501.80, £ 4,051.62, ¥ 516,856.66) +
release price (tray)	$ 5,002.00 (€ 4,501.80, £ 4,051.62, ¥ 516,856.66) +
s-spec	SRFFH +
series	W-3200 +
smp max ways	1 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2933 +
tdp	205 W (205,000 mW, 0.275 hp, 0.205 kW) +
technology	CMOS +
thread count	32 +
turbo frequency (1 core)	4,400 MHz (4.4 GHz, 4,400,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +