Editing intel/xeon gold/5215l

{{intel title|Xeon Gold 5215L}}
{{chip
|name=Xeon Gold 5215L
|image=cascade lake sp (front).png
|designer=Intel
|manufacturer=Intel
|model number=5215L
|part number=CD8069504214202
|s-spec=SRFBD
|market=Server
|first announced=April 2, 2019
|first launched=April 2, 2019
|release price (tray)=$4,224.00
|family=Xeon Gold
|series=5200
|locked=Yes
|frequency=2,500 MHz
|turbo frequency1=3,400 MHz
|bus type=DMI 3.0
|bus links=4
|bus rate=8 GT/s
|clock multiplier=25
|cpuid=0x50655
|isa=x86-64
|isa family=x86
|microarch=Cascade Lake
|platform=Purley
|chipset=Lewisburg
|core name=Cascade Lake SP
|core family=6
|core stepping=L1
|process=14 nm
|technology=CMOS
|word size=64 bit
|core count=10
|thread count=20
|max cpus=4
|max memory=4.5 TiB
|tdp=85 W
|package name 1=intel,fclga_3647
}}
'''Xeon Gold 5215L''' is a {{arch|64}} [[deca-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5215L is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 4.5 TiB of hexa-channel DDR4-2666 memory, operates at 2.2 GHz with a TDP of 125 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz.

As indicated by the "''L''" suffix, this model features extended memory support of up to 4.5 TiB of memory.


== Cache ==
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
{{cache size
|l1 cache=640 KiB
|l1i cache=320 KiB
|l1i break=10x32 KiB
|l1i desc=8-way set associative
|l1d cache=320 KiB
|l1d break=10x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=10 MiB
|l2 break=10x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=13.75 MiB
|l3 break=10x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2666
|ecc=Yes
|max mem=4.5 TiB
|controllers=2
|channels=6
|max bandwidth=119.21 GiB/s
|bandwidth schan=19.87 GiB/s
|bandwidth dchan=39.74 GiB/s
|bandwidth qchan=79.47 GiB/s
|bandwidth hchan=119.21 GiB/s
}}

== Expansions ==
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=48
|pcie config=1x16
|pcie config 2=x8
|pcie config 3=x4
}}
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=No
|avx=Yes
|avx2=Yes
|avx512f=Yes
|avx512cd=Yes
|avx512er=No
|avx512pf=No
|avx512bw=Yes
|avx512dq=Yes
|avx512vl=Yes
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx512vnni=Yes
|avx5124vnniw=No
|avx512vpopcntdq=No
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=No
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|bfloat16=No
|tbt1=No
|tbt2=Yes
|tbmt3=No
|bpt=No
|eist=Yes
|sst=Yes
|flex=No
|fastmem=No
|ivmd=Yes
|intelnodecontroller=No
|intelnode=Yes
|kpt=Yes
|ptt=Yes
|intelrunsure=No
|mbe=Yes
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=Yes
|txt=Yes
|ht=Yes
|vpro=Yes
|vtx=Yes
|vtd=Yes
|ept=Yes
|mpx=No
|sgx=No
|securekey=No
|osguard=No
|intqat=No
|dlboost=Yes
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=No
|amdv=No
|amdsme=No
|amdtsme=No
|amdsev=No
|rvi=No
|smt=No
|sensemi=No
|xfr=No
|xfr2=No
|mxfr=No
|amdpb=No
|amdpb2=No
|amdpbod=No
}}

== Frequencies ==
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
{{frequency table
|freq_base=2,500MHz 
|freq_1=3,400MHz 
|freq_2=3,400MHz 
|freq_3=3,200MHz 
|freq_4=3,200MHz 
|freq_5=3,100MHz 
|freq_6=3,100MHz 
|freq_7=3,100MHz 
|freq_8=3,100MHz 
|freq_9=3,000MHz 
|freq_10=3,000MHz 
|freq_avx2_base=2,000MHz 
|freq_avx2_1=3,100MHz 
|freq_avx2_2=3,100MHz 
|freq_avx2_3=2,900MHz 
|freq_avx2_4=2,900MHz 
|freq_avx2_5=2,800MHz 
|freq_avx2_6=2,800MHz 
|freq_avx2_7=2,800MHz 
|freq_avx2_8=2,800MHz 
|freq_avx2_9=2,600MHz 
|freq_avx2_10=2,600MHz 
|freq_avx512_base=1,400MHz 
|freq_avx512_1=2,900MHz 
|freq_avx512_2=2,900MHz 
|freq_avx512_3=2,500MHz 
|freq_avx512_4=2,500MHz 
|freq_avx512_5=1,900MHz 
|freq_avx512_6=1,900MHz 
|freq_avx512_7=1,900MHz 
|freq_avx512_8=1,900MHz 
|freq_avx512_9=1,800MHz 
|freq_avx512_10=1,800MHz 
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5215L - Intel#pcie +
base frequency	2,500 MHz (2.5 GHz, 2,500,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	25 +
core count	10 +
core family	6 +
core name	Cascade Lake SP +
core stepping	L0 + and L1 +
cpuid	0x50655 +
designer	Intel +
family	Xeon Gold +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon gold/5215l +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Deep Learning Boost +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	640 KiB (655,360 B, 0.625 MiB) +
l1d$ description	8-way set associative +
l1d$ size	320 KiB (327,680 B, 0.313 MiB) +
l1i$ description	8-way set associative +
l1i$ size	320 KiB (327,680 B, 0.313 MiB) +
l2$ description	16-way set associative +
l2$ size	10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
l3$ description	11-way set associative +
l3$ size	13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Server +
max cpu count	4 +
max memory	4,718,592 MiB (4,831,838,208 KiB, 4,947,802,324,992 B, 4,608 GiB, 4.5 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
model number	5215L +
name	Xeon Gold 5215L +
package	FCLGA-3647 +
part number	CD8069504214202 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 4,224.00 (€ 3,801.60, £ 3,421.44, ¥ 436,465.92) +
release price (tray)	$ 4,224.00 (€ 3,801.60, £ 3,421.44, ¥ 436,465.92) +
s-spec	SRFBD +
s-spec (qs)	QRGB +
series	5200 +
smp interconnect	UPI +
smp interconnect links	3 +
smp interconnect rate	10.4 GT/s +
smp max ways	4 +
socket	LGA-3647 + and Socket P +
supported memory type	DDR4-2666 +
tdp	85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technology	CMOS +
thread count	20 +
turbo frequency (1 core)	3,400 MHz (3.4 GHz, 3,400,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +