Editing intel/xeon gold/5217

{{intel title|Xeon Gold 5217}}
{{chip
|name=Xeon Gold 5217
|image=cascade lake sp (front).png
|designer=Intel
|manufacturer=Intel
|model number=5217
|part number=CD8069504214302
|s-spec=SRFBF
|market=Server
|first announced=April 2, 2019
|first launched=April 2, 2019
|release price (tray)=$1,522.00
|family=Xeon Gold
|series=5200
|locked=Yes
|frequency=3,000 MHz
|bus type=DMI 3.0
|bus links=4
|bus rate=8 GT/s
|clock multiplier=30
|cpuid=0x50655
|isa=x86-64
|isa family=x86
|microarch=Cascade Lake
|platform=Purley
|chipset=Lewisburg
|core name=Cascade Lake SP
|core family=6
|core stepping=L1
|process=14 nm
|technology=CMOS
|word size=64 bit
|core count=8
|thread count=16
|max cpus=4
|max memory=1 TiB
|tdp=115 W
|package name 1=intel,fclga_3647
}}
'''Xeon Gold 5217''' is a {{arch|64}} [[octa-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5217 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 3 GHz with a TDP of 115 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz.


== Cache ==
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
{{cache size
|l1 cache=512 KiB
|l1i cache=256 KiB
|l1i break=8x32 KiB
|l1i desc=8-way set associative
|l1d cache=256 KiB
|l1d break=8x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=8 MiB
|l2 break=8x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=11 MiB
|l3 break=8x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2666
|ecc=Yes
|max mem=1 TiB
|controllers=2
|channels=6
|max bandwidth=119.21 GiB/s
|bandwidth schan=19.87 GiB/s
|bandwidth dchan=39.74 GiB/s
|bandwidth qchan=79.47 GiB/s
|bandwidth hchan=119.21 GiB/s
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5217 - Intel#pcie +
base frequency	3,000 MHz (3 GHz, 3,000,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	30 +
core count	8 +
core family	6 +
core name	Cascade Lake SP +
core stepping	L0 + and L1 +
cpuid	0x50655 +
designer	Intel +
family	Xeon Gold +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon gold/5217 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Deep Learning Boost +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	512 KiB (524,288 B, 0.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	8-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ description	16-way set associative +
l2$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description	11-way set associative +
l3$ size	11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Server +
max cpu count	4 +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
model number	5217 +
name	Xeon Gold 5217 +
package	FCLGA-3647 +
part number	CD8069504214302 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,522.00 (€ 1,369.80, £ 1,232.82, ¥ 157,268.26) +
release price (tray)	$ 1,522.00 (€ 1,369.80, £ 1,232.82, ¥ 157,268.26) +
s-spec	SRFBF +
s-spec (qs)	QRGC +
series	5200 +
smp interconnect	UPI +
smp interconnect links	3 +
smp interconnect rate	10.4 GT/s +
smp max ways	4 +
socket	LGA-3647 + and Socket P +
supported memory type	DDR4-2666 +
tdp	115 W (115,000 mW, 0.154 hp, 0.115 kW) +
technology	CMOS +
thread count	16 +
turbo frequency (1 core)	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +