Editing intel/xeon platinum/9221

{{intel title|Xeon Platinum 9221}}
{{chip
|name=Xeon Platinum 9221
|image=cascade lake ap (front).png
|designer=Intel
|manufacturer=Intel
|model number=9221
|market=Server
|market 2=HPC
|first announced=April 2, 2019
|first launched=April 2, 2019
|family=Xeon Platinum
|series=9200
|locked=Yes
|frequency=2,100 MHz
|turbo frequency1=3,700 MHz
|bus type=DMI 3.0
|bus links=4
|bus rate=8 GT/s
|clock multiplier=21
|isa=x86-64
|isa family=x86
|microarch=Cascade Lake
|platform=Walker Pass
|chipset=Lewisburg
|core name=Cascade Lake AP
|core family=6
|process=14 nm
|technology=CMOS
|mcp=Yes
|die count=2
|word size=64 bit
|core count=32
|thread count=64
|max cpus=2
|max memory=2 TiB
|tdp=250 W
|package name 1=intel,fcbga_5903
}}
'''Xeon Platinum 9221''' is a [[56-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 9221 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is fabricated on Intel's [[14 nm process]]. It operates at 2.1 GHz with a TDP of 250 W and a {{intel|turbo boost}} of up to 3.7 GHz. This processor supports up to twelve channels of DDR4-2933 memory.

This processor cannot be purchased independently and is only sold as part of Intel's S9200WK Compute Module.

== Cache ==
{{main|intel/microarchitectures/cascade_lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
{{cache size
|l1 cache=2 MiB
|l1i cache=1 MiB
|l1i break=32x32 KiB
|l1i desc=8-way set associative
|l1d cache=1 MiB
|l1d break=32x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=32 MiB
|l2 break=32x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=71.5 MiB
|l3 break=52x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2933
|ecc=Yes
|max mem=2 TiB
|controllers=4
|channels=12
|max bandwidth=262.26 GiB/s
|bandwidth schan=21.86 GiB/s
|bandwidth dchan=43.71 GiB/s
|bandwidth qchan=87.42 GiB/s
|bandwidth ochan=174.84 GiB/s
}}

== Expansions ==
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=40
|pcie config=1x16
|pcie config 2=x8
|pcie config 3=x4
}}
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=No
|avx=Yes
|avx2=Yes
|avx512f=Yes
|avx512cd=Yes
|avx512er=No
|avx512pf=No
|avx512bw=Yes
|avx512dq=Yes
|avx512vl=Yes
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx512vnni=Yes
|avx5124vnniw=No
|avx512vpopcntdq=No
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=No
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|bfloat16=No
|tbt1=No
|tbt2=Yes
|tbmt3=No
|bpt=No
|eist=Yes
|sst=Yes
|flex=No
|fastmem=No
|ivmd=Yes
|intelnodecontroller=Yes
|intelnode=Yes
|kpt=Yes
|ptt=Yes
|intelrunsure=Yes
|mbe=Yes
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=Yes
|txt=Yes
|ht=Yes
|vpro=Yes
|vtx=Yes
|vtd=Yes
|ept=Yes
|mpx=No
|sgx=No
|securekey=No
|osguard=No
|intqat=No
|dlboost=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=No
|amdv=No
|amdsme=No
|amdtsme=No
|amdsev=No
|rvi=No
|smt=No
|sensemi=No
|xfr=No
|xfr2=No
|mxfr=No
|amdpb=No
|amdpb2=No
|amdpbod=No
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Platinum 9221 - Intel#pcie +
base frequency	2,100 MHz (2.1 GHz, 2,100,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	21 +
core count	32 +
core family	6 +
core name	Cascade Lake AP +
designer	Intel +
die count	2 +
family	Xeon Platinum +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon platinum/9221 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	2,048 KiB (2,097,152 B, 2 MiB) +
l1d$ description	8-way set associative +
l1d$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ description	8-way set associative +
l1i$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l2$ description	16-way set associative +
l2$ size	32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
l3$ description	11-way set associative +
l3$ size	71.5 MiB (73,216 KiB, 74,973,184 B, 0.0698 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Server + and HPC +
max cpu count	2 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth	262.26 GiB/s (268,554.24 MiB/s, 281.6 GB/s, 281,599.531 MB/s, 0.256 TiB/s, 0.282 TB/s) +
max memory channels	12 +
microarchitecture	Cascade Lake +
model number	9221 +
name	Xeon Platinum 9221 +
package	FCBGA-5903 +
platform	Walker Pass +
process	14 nm (0.014 μm, 1.4e-5 mm) +
series	9200 +
smp max ways	2 +
supported memory type	DDR4-2933 +
tdp	250 W (250,000 mW, 0.335 hp, 0.25 kW) +
technology	CMOS +
thread count	64 +
turbo frequency (1 core)	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +