Editing intel/xeon d/d-1653n

{{intel title|Xeon D-1653N}}
{{chip
|name=Xeon D-1653N
|image=hewitt lake (front).png
|back image=broadwell de (back).png
|designer=Intel
|manufacturer=Intel
|model number=D-1653N
|market=Server
|market 2=Embedded
|first announced=April 2, 2019
|first launched=April 2, 2019
|release price (tray)=$748.00
|family=Xeon D
|series=D-1600
|locked=Yes
|frequency=2,800 MHz
|turbo frequency1=3,100 MHz
|bus type=DMI 2.0
|clock multiplier=28
|isa=x86-64
|isa family=x86
|microarch=Broadwell
|platform=Grangeville
|core name=Hewitt Lake
|core family=6
|core model=6
|process=14 nm
|transistors=3,200,000,000
|technology=CMOS
|die area=246.24 mm²
|word size=64 bit
|core count=8
|thread count=16
|max cpus=1
|max memory=128 GiB
|tdp=65 W
|package name 1=intel,fcbga_1667
}}
'''Xeon D-1653N''' is a {{arch|64}} [[octa-core]] [[x86]] microserver SoC introduced by [[Intel]] in early [[2019]]. The D-1653N is based on the {{intel|Broadwell|l=arch}} microarchitecture and is fabricated on their [[14 nm process]]. It operates at 2.8 GHz with a TDP of 65 W and a {{intel|turbo boost|turbo frequency}} of 3.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.


== Cache ==
{{main|intel/microarchitectures/broadwell (server)#Memory_Hierarchy|l1=Broadwell § Cache}}
{{cache size
|l1 cache=512 KiB
|l1i cache=256 KiB
|l1i break=8x32 KiB
|l1i desc=8-way set associative
|l1d cache=256 KiB
|l1d break=8x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=2 MiB
|l2 break=8x256 KiB
|l2 desc=8-way set associative
|l2 policy=write-back
|l3 cache=12 MiB
|l3 break=8x1.5 MiB
|l3 desc=16-way set associative
|l3 policy=write-back
}}

== Graphics ==
This SoC has no integrated graphics processing unit.

== Memory controller ==
{{memory controller
|type=DDR4-2400
|ecc=Yes
|max mem=128 GiB
|controllers=1
|channels=2
|max bandwidth=35.76 GiB/s
|bandwidth schan=17.88 GiB/s
|bandwidth dchan=35.76 GiB/s
}}

== Expansions ==
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=24
|pcie config=x16
|pcie config 2=x8
|pcie config 3=x4
}}
{{expansions entry
|type=PCIe
|pcie revision=2.0
|pcie lanes=8
|pcie config=x8
|pcie config 2=x4
}}
{{expansions entry
|type=USB
|usb revision=3.0
|usb ports=4
}}
{{expansions entry
|type=USB
|usb revision=2.0
|usb ports=4
}}
{{expansions entry
|type=SATA
|sata revision=3
|sata ports=6
}}
}}

== Networking ==
{{network
|eth opts=Yes
|10ge=Yes
|10ge ports=4
}}

== Features ==
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=No
|avx=Yes
|avx2=Yes
|avx512f=No
|avx512cd=No
|avx512er=No
|avx512pf=No
|avx512bw=No
|avx512dq=No
|avx512vl=No
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx512vnni=No
|avx5124vnniw=No
|avx512vpopcntdq=No
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=No
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|bfloat16=No
|tbt1=No
|tbt2=Yes
|tbmt3=No
|bpt=No
|eist=Yes
|sst=No
|flex=No
|fastmem=No
|ivmd=No
|intelnodecontroller=No
|intelnode=No
|kpt=No
|ptt=No
|intelrunsure=No
|mbe=No
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=Yes
|txt=Yes
|ht=Yes
|vpro=No
|vtx=Yes
|vtd=Yes
|ept=Yes
|mpx=No
|sgx=No
|securekey=Yes
|osguard=Yes
|intqat=Yes
|dlboost=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=No
|amdv=No
|amdsme=No
|amdtsme=No
|amdsev=No
|rvi=No
|smt=No
|sensemi=No
|xfr=No
|xfr2=No
|mxfr=No
|amdpb=No
|amdpb2=No
|amdpbod=No
|em64t=Yes
|vt-x=Yes
|vt-d=Yes
|sse4=Yes
|sse4_1=Yes
|sse4_2=Yes
|bmi=Yes
|secure key=Yes
|os guard=Yes
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon D-1653N - Intel#pcie +
back image	+
base frequency	2,800 MHz (2.8 GHz, 2,800,000 kHz) +
bus type	DMI 2.0 +
clock multiplier	28 +
core count	8 +
core family	6 +
core model	6 +
core name	Hewitt Lake +
core stepping	A1 +
designer	Intel +
die area	246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) +
family	Xeon D +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon d/d-1653n +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Integrated QuickAssist Technology +, Intel VT-d +, Intel VT-x +, OS Guard +, Secure Key Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has integrated intel quickassist technology	true +
has intel enhanced speedstep technology	true +
has intel secure key technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	512 KiB (524,288 B, 0.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	8-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ description	8-way set associative +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ description	16-way set associative +
l3$ size	12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Embedded + and Server +
max case temperature	344.15 K (71 °C, 159.8 °F, 619.47 °R) +
max cpu count	1 +
max junction temperature	378.15 K (105 °C, 221 °F, 680.67 °R) +
max memory	131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) +
max memory bandwidth	35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels	2 +
max sata ports	6 +
max usb ports	4 +
microarchitecture	Broadwell +
model number	D-1653N +
name	Xeon D-1653N +
package	FCBGA-1667 +
part number	GG8068204235902 +
platform	Grangeville +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 748.00 (€ 673.20, £ 605.88, ¥ 77,290.84) +
release price (tray)	$ 748.00 (€ 673.20, £ 605.88, ¥ 77,290.84) +
s-spec	SRG04 +
series	D-1600 +
smp max ways	1 +
supported memory type	DDR4-2400 +
tdp	65 W (65,000 mW, 0.0872 hp, 0.065 kW) +
technology	CMOS +
thread count	16 +
transistor count	3,200,000,000 +
turbo frequency (1 core)	3,100 MHz (3.1 GHz, 3,100,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +