Editing intel/xeon silver/4214y

{{intel title|Xeon Silver 4214M}}
{{chip
|future=Yes
|name=Xeon Silver 4214M
|image=skylake sp (basic).png
|designer=Intel
|manufacturer=Intel
|model number=4214M
|market=Server
|first announced=2019
|first launched=2019
|family=Xeon Silver
|series=4000
|locked=Yes
|frequency=2,200 MHz
|clock multiplier=22
|isa=x86-64
|isa family=x86
|microarch=Cascade Lake
|platform=Purley
|chipset=Lewisburg
|core name=Cascade Lake SP
|core family=6
|process=14 nm
|technology=CMOS
|word size=64 bit
|core count=10
|thread count=20
|max cpus=2
|tcase min=0 °C
|tcase max=78 °C
|package module 1={{packages/intel/fclga-3647}}
}}
'''Xeon Silver 4214M''' is a {{arch|64}} [[dodeca-core]] [[x86]] dual-socket mid-range performance server microprocessor set to be introduced by [[Intel]] in early 2019. The Silver 4214M, which is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.2 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to ? GHz, supports up ? GiB of hexa-channel DDR4-2400 ECC memory.


{{unknown features}}


== Cache ==
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
{{cache size
|l1 cache=768 KiB
|l1i cache=384 KiB
|l1i break=12x32 KiB
|l1i desc=8-way set associative
|l1d cache=384 KiB
|l1d break=12x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=12 MiB
|l2 break=12x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=16.5 MiB
|l3 break=12x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2400
|ecc=Yes
|max mem=768 GiB
|controllers=2
|channels=6
|max bandwidth=107.3 GiB/s
|bandwidth schan=17.88 GiB/s
|bandwidth dchan=35.76 GiB/s
|bandwidth qchan=71.53 GiB/s
|bandwidth hchan=107.3 GiB/s
}}

== Expansions ==
{{expansions
| pcie revision      = 3.0
| pcie lanes         = 48
| pcie config        = x16
| pcie config 2      = x8
| pcie config 3      = x4
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=No
|avx=Yes
|avx2=Yes
|avx512f=Yes
|avx512cd=Yes
|avx512er=No
|avx512pf=No
|avx512bw=Yes
|avx512dq=Yes
|avx512vl=Yes
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx5124vnniw=No
|avx512vpopcntdq=No
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=No
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|tbt1=No
|tbt2=Yes
|tbmt3=No
|bpt=No
|eist=Yes
|sst=Yes
|flex=No
|fastmem=No
|ivmd=Yes
|intelnode=Yes
|kpt=Yes
|ptt=Yes
|mbe=Yes
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=Yes
|txt=Yes
|ht=Yes
|vpro=Yes
|vtx=Yes
|vtd=No
|ept=Yes
|mpx=No
|sgx=No
|securekey=No
|osguard=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=No
|amdv=No
|amdsme=No
|amdtsme=No
|amdsev=No
|rvi=No
|smt=No
|sensemi=No
|xfr=No
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Silver 4214Y - Intel#pcie +
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
chipset	Lewisburg +
clock multiplier	22 +
core count	12 +
core family	6 +
core name	Cascade Lake SP +
core stepping	L0 + and L1 +
designer	Intel +
family	Xeon Silver +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon silver/4214y +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Deep Learning Boost +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	768 KiB (786,432 B, 0.75 MiB) +
l1d$ description	8-way set associative +
l1d$ size	384 KiB (393,216 B, 0.375 MiB) +
l1i$ description	8-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	16-way set associative +
l2$ size	12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description	11-way set associative +
l3$ size	16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	350.15 K (77 °C, 170.6 °F, 630.27 °R) +
max cpu count	2 +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	4214Y +
name	Xeon Silver 4214Y +
package	FCLGA-3647 +
part number	CD8069504294401 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 768.00 (€ 691.20, £ 622.08, ¥ 79,357.44) +
release price (tray)	$ 768.00 (€ 691.20, £ 622.08, ¥ 79,357.44) +
s-spec	SRFDG +
s-spec (qs)	QRHY +
series	4200 +
smp interconnect	UPI +
smp interconnect links	2 +
smp interconnect rate	9.6 GT/s(qs) +
smp max ways	2 +
socket	LGA-3647 + and Socket P +
supported memory type	DDR4-2400 +
tdp	85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technology	CMOS +
thread count	24 +
turbo frequency (1 core)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +