Editing intel/microarchitectures/cascade lake

{{intel title|Cascade Lake|arch}}
{{microarchitecture
|atype=CPU
|name=Cascade Lake
|designer=Intel
|manufacturer=Intel
|introduction=2018
|process=14 nm
|type=Superscalar
|oooe=Yes
|speculative=Yes
|renaming=Yes
|stages min=14
|stages max=19
|isa=x86-64
|extension=MOVBE
|extension 2=MMX
|extension 3=SSE
|extension 4=SSE2
|extension 5=SSE3
|extension 6=SSSE3
|extension 7=SSE4.1
|extension 8=SSE4.2
|extension 9=POPCNT
|extension 10=AVX
|extension 11=AVX2
|extension 12=AES
|extension 13=PCLMUL
|extension 14=FSGSBASE
|extension 15=RDRND
|extension 16=FMA3
|extension 17=F16C
|extension 18=BMI
|extension 19=BMI2
|extension 20=VT-x
|extension 21=VT-d
|extension 22=TXT
|extension 23=TSX
|extension 24=RDSEED
|extension 25=ADCX
|extension 26=PREFETCHW
|extension 27=CLFLUSHOPT
|extension 28=XSAVE
|extension 29=SGX
|extension 30=MPX
|extension 31=AVX-512
|l1i=32 KiB
|l1i per=core
|l1i desc=8-way set associative
|l1d=32 KiB
|l1d per=core
|l1d desc=8-way set associative
|l2=1 MiB
|l2 per=core
|l2 desc=16-way set associative
|l3=1.375 MiB
|l3 per=core
|l3 desc=11-way set associative
|core name=Cascade Lake X
|core name 2=Cascade Lake SP
|core name 3=Cascade Lake AP
|predecessor=Skylake (server)
|predecessor link=intel/microarchitectures/skylake (server)
|successor=Cooper Lake
|successor link=intel/microarchitectures/cooper lake
|contemporary=Coffee Lake
|contemporary link=intel/microarchitectures/coffee lake
}}
'''Cascade Lake''' ('''CSL'''/'''CLX''') is [[Intel]]'s successor to {{\\|Skylake (server)|Skylake}}, a [[14 nm]] [[microarchitecture]] for enthusiasts and servers. Cascade Lake is the "Optimization" phase as part of Intel's {{intel|PAO}} model.

For desktop enthusiasts, Cascade Lake is branded {{intel|Core i7}}, and {{intel|Core i9}} processors (under the {{intel|Core X}} series). For scalable server class processors, Intel branded it as {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}}.

== Codenames ==
{| class="wikitable"
|-
! Core !! Abbrev !! Target
|-
| {{intel|Cascade Lake X|l=core}} || CSL-X || High-end desktops & enthusiasts market
|-
| {{intel|Cascade Lake W|l=core}} || CSL-W || Enterprise/Business workstations
|-
| {{intel|Cascade Lake SP|l=core}} || CSL-SP || Server Scalable Processors
|-
| {{intel|Cascade Lake AP|l=core}} || CSL-AP || Server Advanced Processors
|}

== Brands ==
Cascade Lake is sold under eight different families.

{{future information}}

{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
|-
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="7" | Differentiating Features
|-
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{x86|AVX-512}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
|-
| [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || style="text-align: left;" | Enthusiasts/High Performance ({{intel|Skylake X|X|l=core}}) || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
|-
| [[File:core i9x logo.png|50px|link=intel/core_i9]] || {{intel|Core i9}} || style="text-align: left;" | Enthusiasts/High Performance || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
|-
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="7" | Differentiating Features
|-
! Cores !! {{intel|Hyper-Threading|HT}} !! {{intel|Turbo Boost|TBT}} !! {{x86|AVX-512}} !! AVX-512 Units !! {{intel|Ultra Path Interconnect|UPI}} links !! Scalability
|-
| [[File:xeon logo (2015).png|50px|link=intel/xeon d]] || {{intel|Xeon D}} || style="text-align: left;" | Dense servers / edge computing || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 1 || colspan="2" {{tchk|no}}
|-
| [[File:xeon logo (2015).png|50px|link=intel/xeon w]] || {{intel|Xeon W}} || style="text-align: left;" | Business workstations || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2 || colspan="2" {{tchk|no}}
|-
| [[File:xeon bronze (2017).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || ?-? || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} || 1 || 2 || Up to 2
|-
| [[File:xeon silver (2017).png|50px]] || {{intel|Xeon Silver}} || style="text-align: left;" | Mid-range performance / <br>Efficient lower power || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 1 || 2 || Up to 2
|-
| rowspan="2" | [[File:xeon gold (2017).png|50px]] || {{intel|Xeon Gold}} 5000 || style="text-align: left;" | High performance || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 1 || 2 || Up to 4
|-
| {{intel|Xeon Gold}} 6000 || style="text-align: left;" | Higher performance || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2  || 3 || Up to 4
|-
| [[File:xeon platinum (2017).png|50px]] || {{intel|Xeon Platinum}} || style="text-align: left;" | Highest performance / flexibility || ?-? || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2 || 3 || Up to 8
|}

== Release Dates ==
Cascade Lake is expected to be released in late 2018.

== Process Technology ==
Cascade Lake is fabricated on Intel's enhanced [[14 nm process]].

== Architecture ==
As with {{\\|Skylake (server)|Skylake}}, Cascade Lake is also based on the {{intel|Purley|l=platform}} platform and is designed as a drop-in upgrade.
=== Key changes from {{\\|Skylake (server)|Skylake}} ===
* Core
** Security
*** Fix for {{cve|CVE-2017-5715}} (Spectre, Variant 2)
*** Fix for {{cve|CVE-2017-5754}} (Meltdown, Variant 3)
* Package
** Selected SKUs with Arria 10 FPGAs in a [[MCP]]
* Memory
** Support for up to 3 TiB per socket (up from 1.5 TiB)
** Support for DDR-T / Optane DIMMs
{{expand list}}
====New instructions ====
Cascade Lake introduced a number of {{x86|extensions|new instructions}}:

* {{x86|avx-512/vnni|<code>AVX-512 VNNI</code>}} - AVX-512 Vector Neural Network Instructions

=== Block Diagram ===
{{empty section}}


== All Cascade Lake Chips ==
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           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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{{comp table start}}
<table class="comptable sortable tc6 tc7 tc14 tc15">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="24">List of Cascade Lake Processors</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="2">Frequency/{{intel|Turbo Boost|Turbo}}</th><th>Mem</th><th colspan="7">Major Feature Diff</th></tr>
{{comp table header 1|cols=Launched, Price, Family, Core Name, Cores, Threads, %L2$, %L3$, TDP, %Frequency, %Max Turbo, Max Mem, Turbo, SMT}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Uniprocessors]]</th></tr>
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Cascade Lake]] [[max cpu count::1]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=16:15
 |mainlabel=-
 |limit=200
}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Multiprocessors]] (2-way)</th></tr>
{{#ask:
 [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Cascade Lake]] [[max cpu count::2]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=16:15
 |mainlabel=-
 |limit=60
}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Multiprocessors]] (4-way)</th></tr>
{{#ask:
 [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Cascade Lake]] [[max cpu count::4]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=16:15
 |mainlabel=-
 |limit=60
}}
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Multiprocessors]] (8-way)</th></tr>
{{#ask:
 [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Cascade Lake]] [[max cpu count::8]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=16:15
 |mainlabel=-
 |limit=60
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Cascade Lake]]}}
</table>
{{comp table end}}
codename	Cascade Lake +
core count	2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 +, 28 +, 32 +, 48 + and 56 +
designer	Intel +
first launched	2019 +
full page name	intel/microarchitectures/cascade lake +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Cascade Lake +
pipeline stages (max)	19 +
pipeline stages (min)	14 +
process	14 nm (0.014 μm, 1.4e-5 mm) +