Editing hisilicon/kunpeng/hi1610

{{hisilicon title|Hi1610}}
{{chip
|name=Hi1610
|no image=Yes
|designer=HiSilicon
|designer 2=ARM Holdings
|manufacturer=TSMC
|model number=Hi1610
|market=Server
|first announced=2015
|first launched=2015
|family=Hi16xx
|frequency=2,100 MHz
|isa=ARMv8
|isa family=ARM
|microarch=Cortex-A57
|core name=Cortex-A57
|process=16 nm
|technology=CMOS
|word size=64 bit
|core count=16
|thread count=16
|max cpus=1
|max memory=128 GiB
}}
'''Hi1610''' is a [[hexadeca-core]] {{arch|64}} [[ARM]] server microprocessor introduced by HiSilicon in late-2015. Fabricated by [[TSMC]] on a [[16 nm process]], this chip incorporates 16 {{armh|Cortex-A57}} cores operating at 2.1 GHz. The Hi1610 supports up to 128 GiB of dual-channel DDR4-1866 memory.

== Cache ==
{{main|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A57 § Cache}}
{{cache size
|l1 cache=1.25 MiB
|l1i cache=768 MiB
|l1i break=16x48 KiB
|l1i desc=8-way set associative
|l1d cache=512 KiB
|l1d break=16x32 KiB
|l1d desc=8-way set associative
|l2 cache=4 MiB
|l2 break=16x256 KiB
|l2 desc=8-way set associative
|l3 cache=16 MiB
|l3 break=16x1 MiB
|l3 desc=16-way set associative
}}

== Memory controller ==
{{memory controller
|type=DDR4-1866
|ecc=Yes
|max mem=256 GiB
|controllers=1
|channels=2
|width=64 bit
|max bandwidth=55.63 GiB/s
|bandwidth schan=13.91 GiB/s
|bandwidth dchan=27.81 GiB/s
}}

== Expansions ==
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=16
|pcie config=2x8
}}
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Hi1610 - HiSilicon#pcie +
base frequency	2,100 MHz (2.1 GHz, 2,100,000 kHz) +
core count	16 +
core name	Cortex-A57 +
designer	HiSilicon + and ARM Holdings +
family	Hi16xx +
first announced	2015 +
first launched	2015 +
full page name	hisilicon/kunpeng/hi1610 +
has ecc memory support	true +
instance of	microprocessor +
isa	ARMv8 +
isa family	ARM +
l1$ size	1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	512 KiB (524,288 B, 0.5 MiB) +
l1i$ description	8-way set associative +
l1i$ size	768 KiB (786,432 B, 0.75 MiB) +
l2$ description	8-way set associative +
l2$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description	16-way set associative +
l3$ size	16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
ldate	2015 +
manufacturer	TSMC +
market segment	Server +
max cpu count	2 +
max memory	131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) +
max memory bandwidth	55.63 GiB/s (56,965.12 MiB/s, 59.732 GB/s, 59,732.258 MB/s, 0.0543 TiB/s, 0.0597 TB/s) +
max memory channels	2 +
microarchitecture	Cortex-A57 +
model number	Hi1610 +
name	Hi1610 +
process	16 nm (0.016 μm, 1.6e-5 mm) +
smp max ways	2 +
supported memory type	DDR4-1866 +
technology	CMOS +
thread count	16 +
used by	HiSilicon D02 +
word size	64 bit (8 octets, 16 nibbles) +