Editing cavium/thunderx2/cn9965

{{cavium title|ThunderX2 CN9965}}
{{chip
|name=ThunderX2 CN9965
|no image=Yes
|designer=Cavium
|manufacturer=TSMC
|model number=CN9965
|part number=CN9965-2500LG4077-Y21-G
|part number 2=CN9965-2400LG4077-Y21-G
|part number 3=CN9965-2300LG4077-Y21-G
|part number 4=CN9965-2200LG4077-Y21-G
|part number 5=CN9965-2100LG4077-Y21-G
|part number 6=CN9965-2000LG4077-Y21-G
|market=Server
|first announced=May 7, 2018
|first launched=May 7, 2018
|family=ThunderX2
|frequency=1,800 MHz
|frequency 2=2,000 MHz
|frequency 3=2,100 MHz
|frequency 4=2,200 MHz
|isa=ARMv8.1
|isa family=ARM
|microarch=Vulcan
|process=16 nm
|technology=CMOS
|word size=64 bit
|core count=20
|thread count=40
|max cpus=2
|max memory=2 TiB
|package name 1=cavium,fclga_4077
}}
'''ThunderX2 CN9965''' is a {{arch|64}} [[icosa-core]] high-performance [[ARM]] server microprocessor introduced by [[Cavium]] in mid-[[2018]]. The microprocessor, which is based on the {{cavium|Vulcan|l=arch}} microarchitecture, is fabricated on [[TSMC]]'s [[16 nm process]]. Depending on the exact SKU, the CN9965 operates between 1.8 GHz and 2.5 GHz and supports up to quad-/hexa-channel DDR4-2666 memory.

== Cache ==
{{main|cavium/microarchitectures/vulcan#Memory_Hierarchy|l1=Vulcan § Cache}}
{{cache size
|l1 cache=1.25 MiB
|l1i cache=640 KiB
|l1i break=20x32 KiB
|l1i desc=8-way set associative
|l1d cache=640 KiB
|l1d break=20x32 KiB
|l1d desc=8-way set associative
|l2 cache=5 MiB
|l2 break=20x256 KiB
|l2 desc=8-way set associative
|l3 cache=20 MiB
|l3 break=20x1 MiB
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	ThunderX2 CN9965 - Cavium#pcie +
base frequency	1,800 MHz (1.8 GHz, 1,800,000 kHz) +, 2,000 MHz (2 GHz, 2,000,000 kHz) +, 2,100 MHz (2.1 GHz, 2,100,000 kHz) +, 2,200 MHz (2.2 GHz, 2,200,000 kHz) +, 2,300 MHz (2.3 GHz, 2,300,000 kHz) +, 2,400 MHz (2.4 GHz, 2,400,000 kHz) + and 2,500 MHz (2.5 GHz, 2,500,000 kHz) +
core count	20 +
designer	Cavium +
family	ThunderX2 +
first announced	May 7, 2018 +
first launched	May 7, 2018 +
full page name	cavium/thunderx2/cn9965 +
has ecc memory support	true +
instance of	microprocessor +
isa	ARMv8.1 +
isa family	ARM +
l1$ size	1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	640 KiB (655,360 B, 0.625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	640 KiB (655,360 B, 0.625 MiB) +
l2$ description	8-way set associative +
l2$ size	5 MiB (5,120 KiB, 5,242,880 B, 0.00488 GiB) +
l3$ size	20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
ldate	May 7, 2018 +
manufacturer	TSMC +
market segment	Server +
max cpu count	2 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
max sata ports	2 +
max usb ports	2 +
microarchitecture	Vulcan +
model number	CN9965 +
name	ThunderX2 CN9965 +
package	FCLGA-4077 +
part number	CN9965-2500LG4077-Y21-G +, CN9965-2400LG4077-Y21-G +, CN9965-2300LG4077-Y21-G +, CN9965-2200LG4077-Y21-G +, CN9965-2100LG4077-Y21-G +, CN9965-2000LG4077-Y21-G + and CN9965-1800LG4077-Y21-G +
process	16 nm (0.016 μm, 1.6e-5 mm) +
smp max ways	2 +
supported memory type	DDR4-2666 +
technology	CMOS +
thread count	40 +
word size	64 bit (8 octets, 16 nibbles) +