Editing movidius/sabre

{{movidius title|SABRE}}
{{chip
|name=SABRE
|no image=Yes
|designer=Movidius
|manufacturer=TSMC
|model number=SABRE
|market=Embedded
|market 2=Mobile
|frequency=180 MHz
|isa=SPARC V8
|isa family=SPARC
|isa 2=SHAVE
|isa 2 family=SHAVE
|microarch=LEON3
|microarch 2=SHAVE v2.0
|process=65 nm
|technology=CMOS
|word size=32 bit
|core count=9
|thread count=9
}}
'''SABRE''' was a test microprocessor designed by [[Movidius]] for the [[acceleration]] of machine vision. The SABRE microprocessor eventually lead to the production definition of the {{movidius|Myriad|Myriad 1}} line of vision accelerators.

== Overview ==
SABRE is capable of 20 GLOPS at low 100s mW of power through the use of 9 execution units consisting of a [[SPARC]] {{sparc|V8}} [[LEON3]] core and 8 additional {{movidius|SHAVE v2.0|l=arch}} cores.

The test platform consisted of a  [[Samsung]] 6410 [[daughtercard]] which incoluded an [[S3C6410X]] processor ([[ARM11]]) and a Movidius MV0108 SABRE daughtercard which had the SABRE processor.

[[File:movidius sabre test board.png|500px]]

== Block diagram ==
:[[File:movidius sabre block diagram.png|500px]]

== References ==
* Tite, Teodor, et al. "moviOS: a Real-Time Multiprocessor Operating System for Multimedia Applications."
* [https://www.movidius.com/news/happy-10th-birthday-movidius Happy 10th Birthday Movidius]
base frequency	180 MHz (0.18 GHz, 180,000 kHz) +
core count	9 +
designer	Movidius +
full page name	movidius/sabre +
instance of	microprocessor +
isa	SPARC V8 + and SHAVE +
isa family	SPARC + and SHAVE +
ldate	1900 +
manufacturer	TSMC +
market segment	Embedded + and Mobile +
microarchitecture	LEON3 + and SHAVE v2.0 +
model number	SABRE +
name	SABRE +
process	65 nm (0.065 μm, 6.5e-5 mm) +
technology	CMOS +
thread count	9 +
word size	32 bit (4 octets, 8 nibbles) +