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From WikiChip
Editing intel/microarchitectures/goldmont plus
Revision as of 14:10, 13 December 2017 by 175.137.170.60 (talk) (https://www.anandtech.com/show/12146/intel-launches-gemini-lake-pentium-silver-and-celeron-socs-new-cpu-media-features "Intel also confirmed the microarchitecture is a three-wide decode, the same as Goldmont" Removing 4 way decode for now)
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Retrieved from "https://en.wikichip.org/wiki/intel/microarchitectures/goldmont_plus"
Facts about "Goldmont Plus - Microarchitectures - Intel"
codename | Goldmont Plus + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | December 11, 2017 + |
full page name | intel/microarchitectures/goldmont plus + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Goldmont Plus + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |