Editing intel/etann

{{intel title|ETANN}}
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'''ETANN''' ('''Electronically Trainable Analog Neural Network''') was the [[first]] commercial [[neural processor]], introduced by [[Intel]] in [[1992]]. Implemented on a [[1.0 µm process]], this chip incorporated 64 analog neurons and 10,240 analog synapses.

== Overview ==
The ETANN was originally announced at the [[1989]] International Joint Conference on Neural Networks (IJCNN). The chip was implemented using an analog nonvolatile floating gate technology on Intel's CHMOS-III 1µm nonvolatile memory technology. The chip  integrates a total of 64 analog neurons and 1024 analog nonvolatile synapses. The network calculated the [[dot product]] between the 64x64 nonvolatile EEPROM analog synaptic weight array and a 64-element analog input vector. The chip was reported the calculations to exceed 1.3 billion interconnections per second.

== Die ==
* CHMOS-III 1µm nonvolatile memory technology
* 93.15 mm² die size
** 8.1 mm x 11.5 mm

Floor plan:

::[[File:ETANN floor plan.png|500px]]
core voltage	5 V (50 dV, 500 cV, 5,000 mV) +
designer	Intel +
die area	93.15 mm² (0.144 in², 0.932 cm², 93,150,000 µm²) +
die length	8.1 mm (0.81 cm, 0.319 in, 8,100 µm) +
die width	11.5 mm (1.15 cm, 0.453 in, 11,500 µm) +
first announced	1989 +
first launched	1989 +
full page name	intel/etann +
instance of	microprocessor +
ldate	1989 +
manufacturer	Intel +
market segment	Artificial Intelligence +
model number	80170NX +
name	ETANN +
part number	80170NX +
power dissipation	2 W (2,000 mW, 0.00268 hp, 0.002 kW) +
power dissipation (average)	1.5 W (1,500 mW, 0.00201 hp, 0.0015 kW) +
process	1,000 nm (1 μm, 0.001 mm) +