Editing pezy/pezy-scx/pezy-sc2

{{pezy title|PEZY-SC2}}
{{mpu
|future=Yes
|name=PEZY-SC2
|no image=Yes
|designer=PEZY
|manufacturer=TSMC
|model number=PEZY-SC2
|market=Supercomputer
|first announced=2015
|first launched=2016
|family=PEZY-SCx
|frequency=1,000 MHz
|process=16 nm
|technology=CMOS
|die area=620 mm²
|core count=2,048
|power=180 W
|v core=0.8 V
}}
'''PEZY-SC2''' ('''PEZY Super Computer 2''') is third generation [[many-core microprocessor]] developed by [[PEZY]] released in early 2017. The SC2 incorporates 2,048 cores, twice as many cores as its predecessor.

PEZY-SC2 operates at 1 GHz and consume around 200 W while delivering performance in the order of 16.4 TFLOPS (HP), 8.2 TFLOPS (SP), and 4.1 TFLOPS (DP). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's [[16 nm process]].

== Memory controller ==
{{memory controller
|type=DDR4-2666
|ecc=Yes
}}

{{memory controller
|wide-io clock=2,000 MHz
|wide-io width=1,024 bit
|channels=4
|max bandwidth=1.863 TiB/s
}}

== Expansions ==
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=32
|pcie config=x16
|pcie config 2=x8
|pcie config 3=x4
}}
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	PEZY-SC2 - PEZY#pcie +
base frequency	1,000 MHz (1 GHz, 1,000,000 kHz) +
core count	2,048 +
core voltage	0.8 V (8 dV, 80 cV, 800 mV) +
designer	PEZY +
die area	620 mm² (0.961 in², 6.2 cm², 620,000,000 µm²) +
family	PEZY-SCx +
first announced	2015 +
first launched	2017 +
full page name	pezy/pezy-scx/pezy-sc2 +
has ecc memory support	true + and false +
instance of	microprocessor +
l1$ size	768 KiB (786,432 B, 0.75 MiB) + and 12,288 KiB (12,582,912 B, 12 MiB) +
l1d$ description	8-way set associative +
l1d$ size	384 KiB (393,216 B, 0.375 MiB) + and 4,096 KiB (4,194,304 B, 4 MiB) +
l1i$ description	4-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) + and 8,192 KiB (8,388,608 B, 8 MiB) +
l2$ description	8-way set associative +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + and 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description	shared LLC +
l3$ size	40 MiB (40,960 KiB, 41,943,040 B, 0.0391 GiB) +
ldate	3000 +
manufacturer	TSMC +
market segment	Supercomputer +
max memory bandwidth	95.37 GiB/s (97,658.88 MiB/s, 102.403 GB/s, 102,402.758 MB/s, 0.0931 TiB/s, 0.102 TB/s) + and 1,907.712 GiB/s (1,953,497.088 MiB/s, 2,048.39 GB/s, 2,048,390.163 MB/s, 1.863 TiB/s, 2.048 TB/s) +
max memory channels	4 +
model number	PEZY-SC2 +
name	PEZY-SC2 +
peak flops (double-precision)	4,096,000,000,000 FLOPS (4,096,000,000 KFLOPS, 4,096,000 MFLOPS, 4,096 GFLOPS, 4.096 TFLOPS, 0.0041 PFLOPS, 4.096e-6 EFLOPS, 4.096e-9 ZFLOPS) +
peak flops (half-precision)	16,384,000,000,000 FLOPS (16,384,000,000 KFLOPS, 16,384,000 MFLOPS, 16,384 GFLOPS, 16.384 TFLOPS, 0.0164 PFLOPS, 1.6384e-5 EFLOPS, 1.6384e-8 ZFLOPS) +
peak flops (single-precision)	8,192,000,000,000 FLOPS (8,192,000,000 KFLOPS, 8,192,000 MFLOPS, 8,192 GFLOPS, 8.192 TFLOPS, 0.00819 PFLOPS, 8.192e-6 EFLOPS, 8.192e-9 ZFLOPS) +
power dissipation	180 W (180,000 mW, 0.241 hp, 0.18 kW) +
power dissipation (average)	130 W (130,000 mW, 0.174 hp, 0.13 kW) +
process	16 nm (0.016 μm, 1.6e-5 mm) +
supported memory type	DDR4-3200 +
technology	CMOS +
thread count	16,384 +