Editing intel/microarchitectures/sandy bridge (client)

{{intel title|Sandy Bridge|arch}}
{{microarchitecture
|atype=CPU
|name=Sandy Bridge
|designer=Intel
|manufacturer=Intel
|introduction=September 13, 2010
|phase-out=November, 2012
|process=32 nm
|cores=2
|cores 2=4
|type=Superscalar
|type 2=Superpipeline
|oooe=Yes
|speculative=Yes
|renaming=Yes
|stages min=14
|stages max=19
|decode=4-way
|isa=x86-16
|isa 2=x86-32
|isa 3=x86-64
|predecessor=Westmere
|predecessor link=intel/microarchitectures/westmere
|successor=Ivy Bridge
|successor link=intel/microarchitectures/ivy bridge
}}
'''Sandy Bridge''' ('''SNB''') '''Client Configuration''', formerly '''Gesher''', is [[Intel]]'s successor to {{\\|Nehalem}}, a [[32 nm process]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. Sandy Bridge is the "Tock" phase as part of Intel's {{intel|Tick-Tock}} model which added a significant number of enhancements and features. The microarchitecture was predominantly developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]].

For desktop and mobile, Sandy Bridge is branded as 2nd Generation Intel {{intel|Core i3}}, {{intel|Core i5}}, {{intel|Core i7}} processors. For workstations it's branded as first generation {{intel|Xeon E3}}.

== Etymology ==
[[File:intel gesher.jpg|left|150px]]
''Sandy Bridge'' was originally called ''Gesher'' which literally means "bridge" in Hebrew. The name was requested to be changed by upper management after a meeting between the development group and analysts brought up that it might be a bad idea to be associated with a failed political party that was eventually dissolved.

The name ''Sandy Bridge'' consists of the English translation of "Gesher" with "Sandy" possible referring to the fact that silicon comes from sand.

The Logo on the left was Intel's original ("Gesher") logo for the microarchitecture.
{{clear}}

== Codenames ==
{{empty section}}

== Process Technology ==
{{main|intel/microarchitectures/westmere#Process_Technology|l1=Westmere § Process Technology}}
Sandy Bridge uses the same [[32 nm process]] used for the Westmere microarchitecture for all mainstream consumer parts.

== Architecture ==
Sandy Bridge's features an entirely new architecture with a brand new core design which is both more performent and more power efficient. Sandy Bridge provides considerable higher integration verses its {{intel|microarchitectures|predecessors}}.
=== Key changes from {{\\|Westmere}} ===
[[File:sandy bridge buffer window.png|right|350px]]
* Entirely brand new microarchitecture
* Chipset
** {{intel|Ibex Peak|l=chipset}} → {{intel|Cougar Point}}
** {{intel|Socket H}} (LGA-1156) → {{intel|Socket H2}} (LGA-1155)
* Integrated Graphics
** Integrated graphics is now integrated on the same die (previously was on a second die)
** Dropped {{intel|QPI}} controller which linked the two dies
* IMC
** Integrated on-die is now integrated on the same die (previously was on a second die)
** Dropped {{intel|QPI}} controller which linked the two dies
{{expand section}}

=== Block Diagram ===
====== Individual Core ======
[[File:sandy bridge block diagram.svg|900px]]

==Overview ==
[[File:sandy bridge overview.svg|right|450px]]
Sandy Bridge was an entirely new microarchitecture which combines some of the improvements that were implemented in {{\\|NetBurst}} along with the original {{\\|P6}} design. In addition to the new core design, Sandy Bridge took advantage of Intel's [[32 nm process]] which enabled the integration all the components of the chip on a single die, including the [[integrated graphics]] and the [[integrated memory controller]]. Previously (e.g., {{\\|Nehalem}}) the integrated graphics and the memory interface were fabricated on a separate die which was packaged together and communicated over Intel's {{intel|QuickPath Interconnect}} (QPI).

Sandy Bridge introduced a number of performance features that brought better-than-linear performance/power as well as a number of enhancements that improved performance while saving power. Intel introduced a number of new vector computation security instructions which improved [[floating point]] performance and throughput as well as speedup the throughput of various encryption algorithms.

The block diagram on the right is a complete [[quad-core]] Sandy Bridge SoC which integrates the {{intel|System Agent}} (SA), the four [[physical cores]], and the integrated graphics. Interconnecting everything is a complex ring on-die which is composed of six agents - one for each core and cache slice, one for the system agent, and one for the graphics. The upper portion of the diagram is the {{intel|System Agent}} (SA) which incorporates the display controller, the memory controller, and the various I/O interfaces. Sandy Bridge incorporates 20 [[PCIe]] 2.0 lanes - x4 are used by the {{intel|DMI}} with the other x16 lanes designed for a dedicated GPU. The memory controller supports up to dual-channel DDR3-1333 (depending on model).

Sandy Bridge integrated four cores (or two for lower end) on die, each including its own [[last level cache]] (LLC) slice. Sandy Bridge improves the cache with higher bandwidth and lower power. The individual cores have undergone a total redesign which improved both performance and power.

== Core ==
Sandy Bridge can be considered the first brand new microarchitecture since the introduction of {{\\|NetBurst}} and {{\\|P6}} prior. Sandy Bridge went back to the drawing board and incorporated many of beneficial elements from {{\\|P6}} as well as {{\\|NetBurst}}. While NetBurst ended up being a seriously flawed architecture, its design was driven by a number of key innovations which were re-implemented and enhanced in Sandy Bridge. This is different from earlier architectures (i.e., {{\\|Core}} through {{\\|Nehalem}}) which were almost exclusively enhancements of {{\\|P6}} with nothing inherited from P4. Every aspect of the core was improved over its predecessors with very functional block being improved.

[[File:intel uarch evolution p5 to sandy.svg|1300px]] 


{{expand section}}

== Die ==
Quad-core Sandy Bridge die:
: [[File:sandy bridge (quad-core).jpg|850px]]

: [[File:sandy bridge (quad-core) (annotated).png|850px]]
* 1,160,000,000 transistors
* [[32 nm process]]
* 216 mm<sup>2</sup>
* 4 CPU cores
* 1 GPU core
** 12 EUs
== Cores ==
{{empty section}}

== All Sandy Bridge Chips ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
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           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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<table class="wikitable sortable">
<tr><th colspan="12" style="background:#D6D6FF;">Sandy Bridge Chips</th></tr>
<tr><th colspan="9">Main processor</th><th colspan="3">IGP</th></tr>
<tr><th>Model</th><th>µarch</th><th>Platform</th><th>Core</th><th>Launched</th><th>SDP</th><th>TDP</th><th>Freq</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Max Freq</th></tr>
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Sandy Bridge]]
 |?full page name
 |?model number
 |?microarchitecture
 |?platform
 |?core name
 |?first launched
 |?sdp
 |?tdp
 |?base frequency
 |?max memory
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |format=template
 |template=proc table 2
 |userparam=13
 |mainlabel=-
}}
<tr><th colspan="12">Count: {{#ask:[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Sandy Bridge]]|format=count}}</th></tr>
</table>
codename	Sandy Bridge (client) +
core count	2 + and 4 +
designer	Intel +
first launched	September 13, 2010 +
full page name	intel/microarchitectures/sandy bridge (client) +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Sandy Bridge (client) +
phase-out	November 2012 +
pipeline stages (max)	19 +
pipeline stages (min)	14 +
process	32 nm (0.032 μm, 3.2e-5 mm) +