Editing renesas/r-car/h2

{{renesas title|R-Car H2}}
{{mpu
|name=R-Car H2
|image=r-car h2.jpg
|designer=Renesas
|designer 2=ARM Holdings
|manufacturer=TSMC
|model number=H2
|part number=R8A7790
|market=Embedded
|first announced=March 25, 2013
|first launched=June, 2014
|family=R-Car
|series=2nd Gen
|frequency=1,500 MHz
|frequency 2=1,000 MHz
|frequency 3=780 MHz
|isa=ARMv7
|isa family=ARM
|isa 2=SuperH
|isa 2 family=SuperH
|microarch=Cortex A15
|microarch 2=Cortex A7
|microarch 3=SH-4A
|core name=Cortex A15
|core name 2=Cortex A7
|core name 3=SH-4A
|process=28 nm
|technology=CMOS
|word size=32 bit
|core count=9
|thread count=9
|max cpus=1
|v core=1.0 V
|v io=3.3
|v io 2=1.8
|package module 1={{packages/renesas/fcbga-831}}
}}
'''R-Car H2''' is a high-end embedded [[nona-core]] SoC for the automotive industry introduced by [[Renesas]] in early [[2013]]. The H2 incorporates four {{armh|Cortex-A15}} cores operating at 1.5 GHz, four {{armh|Cortex-A7}} cores operating at 1 GHz, and one {{renesas|SH-4A}} core operating at 780 MHz for real-time processing. This SoC incorporates [[Imagination Technologies|Imagination]]'s {{imgtec|PowerVR G6400}} [[GPU]] operating at 550 MHz and supports up to dual-channel DDR3-1600 memory.

== Cache ==
{{main|arm holdings/microarchitectures/cortex-a15#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a7#Memory_Hierarchy|l1=Cortex-A15 § Cache|l2=Cortex-A7 § Cache}}
{{cache size
|l1 cache=576 KiB
|l1i cache=288 KiB
|l1i break=9x32 KiB
|l1d cache=288 KiB
|l1d break=9x32 KiB
|l2 cache=2.5 MiB
}}

== Memory controller ==
{{memory controller
|type=DDR3-1600
|ecc=No
|controllers=1
|channels=2
|width=32 bit
|max bandwidth=11.92 GiB/s
|bandwidth schan=5.96 GiB/s
|bandwidth dchan=11.92 GiB/s
}}

== Expansions ==
* Flash ROM and SRAM, Data bus width: 8 or 16 bits
* PCI Express2.0 (1 lane)
* USB 3.0 Host interface × 1 port (wPHY)
* USB 2.0 Host interface × 3 port (wPHY)
* SD Host interface × 4 ch (SDXC, UHS-I)
* Multimedia card interface × 2 ch
* Serial ATA interface × 2 ch
* I²C bus interface × 8 ch
* Serial communication interface (SCIF) × 10 ch
* Quad serial peripheral interface (QSPI) × 1 ch (for boot)
* Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
* Ethernet controller (IEEE802.3u, RMII, without PHY)

== Graphics ==
{{integrated graphics
| gpu                 = PowerVR G6400
| designer            = Imagination Technologies
| execution units     = 1
| max displays        = 2
| frequency           = 550 MHz
}}

== Features == 
{{arm features
|thumb=No
|thumb2=Yes
|thumbee=Yes
|vfpv1=No
|vfpv2=No
|vfpv3=No
|vfpv3-d16=No
|vfpv3-f16=No
|vfpv4=Yes
|vfpv4-d16=No
|vfpv5=No
|neon=Yes
|jazelle=No
|wmmx=No
|wmmx2=No
}}

== Block Diagram ==
::[[File:r-car h2 block.png|750px]]

== Dev Board ("LAGER") ==
[[File:R-Car H2 dev board.png|right|200px]]
* 210 mm x 180 mm
* R-Car H2
* 68 MiB serial flash memory
* 4 GiB DDR3-DRAM-1600; 1x 64-bit configuration
* RS-232C, UART, USB, SD, LAN, SATA, PCIe , CAN and MLB interfaces (partially via connector)
* HDMI and LVDS display-out
* switches, LEDs, I/O expansion header
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	R-Car H2 - Renesas#package +
base frequency	1,500 MHz (1.5 GHz, 1,500,000 kHz) +, 1,000 MHz (1 GHz, 1,000,000 kHz) + and 780 MHz (0.78 GHz, 780,000 kHz) +
core count	9 +
core name	Cortex A15 +, Cortex A7 + and SH-4A +
core voltage	1 V (10 dV, 100 cV, 1,000 mV) +
designer	Renesas + and ARM Holdings +
family	R-Car +
first announced	March 25, 2013 +
first launched	June 2014 +
full page name	renesas/r-car/h2 +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	PowerVR G6400 +
integrated gpu base frequency	550 MHz (0.55 GHz, 550,000 KHz) +
integrated gpu designer	Imagination Technologies +
integrated gpu execution units	1 +
io voltage	3.3 V (33 dV, 330 cV, 3,300 mV) + and 1.8 V (18 dV, 180 cV, 1,800 mV) +
isa	ARMv7 + and SuperH +
isa family	ARM + and SuperH +
l1$ size	576 KiB (589,824 B, 0.563 MiB) +
l1d$ size	288 KiB (294,912 B, 0.281 MiB) +
l1i$ size	288 KiB (294,912 B, 0.281 MiB) +
l2$ size	2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
ldate	June 2014 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max cpu count	1 +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	2 +
microarchitecture	Cortex A15 +, Cortex A7 + and SH-4A +
model number	H2 +
name	R-Car H2 +
package	FCBGA-831 +
part number	R8A7790 +
process	28 nm (0.028 μm, 2.8e-5 mm) +
series	2nd Gen +
smp max ways	1 +
supported memory type	DDR3-1600 +
technology	CMOS +
thread count	9 +
word size	32 bit (4 octets, 8 nibbles) +