Editing renesas/r-car/e2

{{renesas title|R-Car E2}}
{{mpu
|name=R-Car E2
|image=r-car e2.jpg
|designer=Renesas
|designer 2=ARM Holdings
|manufacturer=TSMC
|model number=E2
|part number=R8A7794
|market=Embedded
|first announced=October 22, 2014
|first launched=June, 2016
|family=R-Car
|series=2nd Gen
|frequency=1,000 MHz
|frequency 2=780 MHz
|isa=ARMv7
|isa family=ARM
|isa 2=SuperH
|isa 2 family=SuperH
|microarch=Cortex-A7
|microarch 2=SH-4A
|core name=Cortex-A7
|core name 2=SH-4A
|process=28 nm
|technology=CMOS
|word size=32 bit
|core count=3
|thread count=3
|max cpus=1
|max memory=2 GiB
|v core=1.0 V
|v io=3.3 V
|v io 2=1.8 V
|package module 1={{packages/renesas/fcbga-501}}
}}
'''R-Car E2''' is an entry-level embedded [[tri-core]] SoC designed by [[Renesas]] for the automotive industry and introduced in late 2014. The E2 incorporates two {{armh|Cortex-A7}} cores operating at 1 GHz along with a {{renesas|SH-4A}} core operating at 780 MHz for real-time processing. This chip includes an [[Imagination Technologies|Imagination]] {{imgtec|PowerVR SGX540}} [[GPU]] operating at 260 MHz and supports up to 2 GiB of dual-channel DDR3-1333 memory.

== Cache ==
{{main|arm holdings/microarchitectures/cortex-a7#Memory_Hierarchy|l1=Cortex-A7 § Cache}}
{{cache size
|l1 cache=192 KiB
|l1i cache=96 KiB
|l1i break=3x32 KiB
|l1d cache=96 KiB
|l1d break=3x32 KiB
|l2 cache=512 KiB
|l2 break=1x512 KiB
}}

== Memory controller ==
{{memory controller
|type=DDR3-1333
|ecc=No
|max mem=2 GiB
|controllers=1
|channels=2
|width=32 bit
|max bandwidth=9.93 GiB/s
|bandwidth schan=4.97 GiB/s
|bandwidth dchan=9.93 GiB/s
}}

== Expansions ==
* Flash ROM and SRAM, Data bus width: 8 or 16 bits
* USB 2.0 host interface × 2 ports (wPHY)
* SD host interface × 3 ch (SDXC, UHS-I)
* Multimedia card interface × 1 ch
* I²C bus interface × 8 ch
* Serial communication interface (SCIF) × 18 ch
* Quad serial peripheral interface (QSPI) × 1 ch (for boot)
* Clock-synchronized serial interface (MSIOF) × 3 ch (SPI/IIS)
* Ethernet AVB controller (IEEE802.1BA/802.1AS/802.1Qav/IEEE1722, GMII/MII, without PHY)
* Ethernet controller (IEEE802.3u, RMII, without PHY)

== Graphics ==
{{integrated graphics
| gpu                 = PowerVR SGX540
| designer            = Imagination Technologies
| execution units     = 1
| max displays        = 2
| frequency           = 260 MHz
}}

== Features == 
{{arm features
|thumb=No
|thumb2=Yes
|thumbee=Yes
|vfpv1=No
|vfpv2=No
|vfpv3=No
|vfpv3-d16=No
|vfpv3-f16=No
|vfpv4=Yes
|vfpv4-d16=No
|vfpv5=No
|neon=Yes
|jazelle=No
|wmmx=No
|wmmx2=No
}}

== Block Diagram ==
::[[File:r-car e2 block.png|750px]]

== Dev Board ("ALT") ==
[[File:R-Car E2 dev board.png|right|200px]]
* 210 mm x 160 mm
* 68 MB serial flash & 8 GByte eMMC memory
* 1 GB DDR3-DRAM-1333; 2 x 16-bit configuration
* RS-232C, UART, 2x USB, SD, LAN, CAN
* EtherAVB PHY Connetor
* Video in (2ch)
* RGB and LVDS display-out
* switches, LEDs, I/O expansion headers
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	R-Car E2 - Renesas#package +
base frequency	1,000 MHz (1 GHz, 1,000,000 kHz) + and 780 MHz (0.78 GHz, 780,000 kHz) +
core count	3 +
core name	Cortex-A7 + and SH-4A +
core voltage	1 V (10 dV, 100 cV, 1,000 mV) +
designer	Renesas + and ARM Holdings +
family	R-Car +
first announced	October 22, 2014 +
first launched	June 2016 +
full page name	renesas/r-car/e2 +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	PowerVR SGX540 +
integrated gpu base frequency	260 MHz (0.26 GHz, 260,000 KHz) +
integrated gpu designer	Imagination Technologies +
integrated gpu execution units	1 +
io voltage	3.3 V (33 dV, 330 cV, 3,300 mV) + and 1.8 V (18 dV, 180 cV, 1,800 mV) +
isa	ARMv7 + and SuperH +
isa family	ARM + and SuperH +
l1$ size	192 KiB (196,608 B, 0.188 MiB) +
l1d$ size	96 KiB (98,304 B, 0.0938 MiB) +
l1i$ size	96 KiB (98,304 B, 0.0938 MiB) +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldate	June 2016 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max cpu count	1 +
max memory	2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth	9.93 GiB/s (10,168.32 MiB/s, 10.662 GB/s, 10,662.256 MB/s, 0.0097 TiB/s, 0.0107 TB/s) +
max memory channels	2 +
microarchitecture	Cortex-A7 + and SH-4A +
model number	E2 +
name	R-Car E2 +
package	FCBGA-501 +
part number	R8A7794 +
process	28 nm (0.028 μm, 2.8e-5 mm) +
series	2nd Gen +
smp max ways	1 +
supported memory type	DDR3-1333 +
technology	CMOS +
thread count	3 +
word size	32 bit (4 octets, 8 nibbles) +