Editing renesas/r-car/m2

{{renesas title|R-Car M2}}
{{mpu
|name=R-Car M2
|image=r-car m2.jpg
|designer=Renesas
|designer 2=ARM Holdings
|manufacturer=TSMC
|model number=M2
|part number=R8A7791
|market=Embedded
|first announced=September 26, 2013
|first launched=June, 2015
|family=R-Car
|series=2nd Gen
|frequency=1,500 MHz
|isa=ARMv7
|isa family=ARM
|isa 2=SuperH
|isa 2 family=SuperH
|microarch=Cortex-A15
|microarch 2=SH-4A
|core name=Cortex-A15
|core name 2=SH-4A
|process=28 nm
|technology=CMOS
|word size=32 bit
|core count=3
|thread count=3
|max cpus=1
|v core=1.03 V
|v io=1.8 V
|v io 2=3.3 V
|package module 1={{packages/renesas/fcbga-831}}
}}
'''R-Car M2''' is a mid-range performance embedded [[tri-core]] SoC designed by [[Renesas]] for the automotive industry and introduced in late 2013. The M2 incorporates two {{armh|Cortex-A15}} cores operating at 1.5 GHz and a third {{renesas|SH-4A}} core for real-time processing. This chip incorporates [[imagination technologies|Imagination]]'s {{imgtec|PowerVR SGX544}} [[GPU]] operating at 520 MHz and supports up to dual-channel DDR3-1600 memory.

== Cache ==
{{main|arm holdings/microarchitectures/cortex-a15#Memory_Hierarchy|l1=Cortex-A15 § Cache}}
{{cache size
|l1 cache=192 KiB
|l1i cache=96 KiB
|l1i break=3x32 KiB
|l1d cache=96 KiB
|l1d break=3x32 KiB
|l2 cache=2 MiB
|l2 break=1x2 MiB
}}

== Memory controller ==
{{memory controller
|type=DDR3-1600
|ecc=No
|controllers=1
|channels=2
|width=32 bit
|max bandwidth=11.92 GiB/s
|bandwidth schan=5.96 GiB/s
|bandwidth dchan=11.92 GiB/s
}}

== Expansions ==
* Flash ROM and SRAM, Data bus width: 8 or 16 bits
* PCI Express2.0 (1 lane)
* USB 3.0 host interface × 1 port (wPHY)
* USB 2.0 host interface × 2 ports (wPHY)
* SD host interface × 3 ch (SDXC, UHS-I)
* Multimedia card interface × 1 ch
* Serial ATA interface × 2 ch
* I²C bus interface × 9 ch
* Serial communication interface (SCIF) × 18 ch
* Quad serial peripheral interface (QSPI) × 1 ch (for boot)
* Clock-synchronized serial interface (MSIOF) × 3 ch (SPI/IIS)
* Ethernet AVB controller (IEEE802.1BA/802.1AS/802.1Qav/IEEE1722, GMII/MII, without PHY)
* Ethernet controller (IEEE802.3u, RMII, without PHY)

== Graphics ==
{{integrated graphics
| gpu                 = PowerVR SGX544
| designer            = Imagination Technologies
| execution units     = 2
| max displays        = 2
| frequency           = 520 MHz
}}

== Features == 
{{arm features
|thumb=No
|thumb2=Yes
|thumbee=Yes
|vfpv1=No
|vfpv2=No
|vfpv3=No
|vfpv3-d16=No
|vfpv3-f16=No
|vfpv4=Yes
|vfpv4-d16=No
|vfpv5=No
|neon=Yes
|jazelle=No
|wmmx=No
|wmmx2=No
}}

== Block Diagram ==
::[[File:r-car m2 block.png|750px]]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	R-Car M2 - Renesas#package +
base frequency	1,500 MHz (1.5 GHz, 1,500,000 kHz) +
core count	3 +
core name	Cortex-A15 + and SH-4A +
core voltage	1.03 V (10.3 dV, 103 cV, 1,030 mV) +
designer	Renesas + and ARM Holdings +
family	R-Car +
first announced	September 26, 2013 +
first launched	June 2015 +
full page name	renesas/r-car/m2 +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	PowerVR SGX544 +
integrated gpu base frequency	520 MHz (0.52 GHz, 520,000 KHz) +
integrated gpu designer	Imagination Technologies +
integrated gpu execution units	2 +
io voltage	1.8 V (18 dV, 180 cV, 1,800 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	ARMv7 + and SuperH +
isa family	ARM + and SuperH +
l1$ size	192 KiB (196,608 B, 0.188 MiB) +
l1d$ size	96 KiB (98,304 B, 0.0938 MiB) +
l1i$ size	96 KiB (98,304 B, 0.0938 MiB) +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	June 2015 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max cpu count	1 +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	2 +
microarchitecture	Cortex-A15 + and SH-4A +
model number	M2 +
name	R-Car M2 +
package	FCBGA-831 +
part number	R8A7791 +
process	28 nm (0.028 μm, 2.8e-5 mm) +
series	2nd Gen +
smp max ways	1 +
supported memory type	DDR3-1600 +
technology	CMOS +
thread count	3 +
word size	32 bit (4 octets, 8 nibbles) +