Editing intel/xeon gold/6136

{{intel title|Xeon Gold 6136}}
{{mpu
|future=Yes
|name=Xeon Gold 6136
|no image=Yes
|image=skylake sp (basic).png
|designer=Intel
|manufacturer=Intel
|model number=6136
|part number=CD8067303405800
|s-spec=SR3B2
|market=Server
|first announced=April 25, 2017
|first launched=July 11, 2017
|release price=$2460.00
|family=Xeon Gold
|series=6000
|locked=Yes
|frequency=3,000 MHz
|turbo frequency1=3,700 MHz
|bus type=DMI 3.0
|bus links=4
|bus rate=8 GT/s
|clock multiplier=30
|isa=x86-64
|isa family=x86
|microarch=Skylake
|platform=Purley
|chipset=Lewisburg
|core name=Skylake SP
|core family=6
|core stepping=H0
|process=14 nm
|technology=CMOS
|word size=64 bit
|core count=12
|thread count=24
|max cpus=4
|max memory=768 GiB
|tdp=150 W
|tcase min=0 °C
|tcase max=85 °C
|package module 1={{packages/intel/fclga-3647}}
}}
'''Xeon Gold 6136''' is a {{arch|64}} [[x86]] [[dodeca-core]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6136 operates at 3.0 GHz


{{unknown features}}

== Cache ==
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
{{cache size
|l1 cache=768 KiB
|l1i cache=384 KiB
|l1i break=12x32 KiB
|l1i desc=8-way set associative
|l1d cache=384 KiB
|l1d break=12x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=12 MiB
|l2 break=12x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=16.5 MiB
|l3 break=10x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=No
|avx=Yes
|avx2=Yes

|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=No
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|tbt1=No
|tbt2=No
|tbmt3=No
|bpt=No
|eist=Yes
|sst=No
|flex=No
|fastmem=No
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=Yes
|txt=No
|ht=Yes
|vpro=Yes
|vtx=Yes
|vtd=Yes
|ept=Yes
|mpx=Yes
|sgx=No
|securekey=No
|osguard=Yes
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=No
|amdv=No
|rvi=No
|smt=No
|sensemi=No
|xfr=No
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 6136 - Intel +, Xeon Gold 6136 - Intel +, Xeon Gold 6136 - Intel +, Xeon Gold 6136 - Intel + and Xeon Gold 6136 - Intel#io +
base frequency	3,000 MHz (3 GHz, 3,000,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	30 +
core count	12 +
core family	6 +
core name	Skylake SP +
core stepping	H0 +
cpuid	0x50654 +
designer	Intel +
family	Xeon Gold +
first announced	April 25, 2017 +
first launched	July 11, 2017 +
full page name	intel/xeon gold/6136 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	768 KiB (786,432 B, 0.75 MiB) +
l1d$ description	8-way set associative +
l1d$ size	384 KiB (393,216 B, 0.375 MiB) +
l1i$ description	8-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	16-way set associative +
l2$ size	12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description	11-way set associative +
l3$ size	24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) +
ldate	July 11, 2017 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	358.15 K (85 °C, 185 °F, 644.67 °R) +
max cpu count	4 +
max dts temperature	103 °C +
max memory	786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Skylake (server) +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature	0 °C +
model number	6136 +
name	Xeon Gold 6136 +
package	FCLGA-3647 +
part number	CD8067303405800 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 2,460.00 (€ 2,214.00, £ 1,992.60, ¥ 254,191.80) +
s-spec	SR3B2 +
s-spec (qs)	QMRX +
series	6100 +
smp interconnect	UPI +
smp interconnect links	3 +
smp interconnect rate	10.4 GT/s +
smp max ways	4 +
socket	LGA-3647 + and Socket P +
supported memory type	DDR4-2666 +
tdp	150 W (150,000 mW, 0.201 hp, 0.15 kW) +
technology	CMOS +
thread count	24 +
turbo frequency (1 core)	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +