Editing intel/xeon gold/5120

{{intel title|Xeon Gold 5120}}
{{mpu
|name=Xeon Gold 5120
|image=skylake sp (basic).png
|designer=Intel
|manufacturer=Intel
|model number=5120
|part number=BX806735120
|part number 2=CD8067303535900
|s-spec=SR3GD
|market=Server
|first announced=July 11, 2017
|first launched=July 11, 2017
|release price=$1555.00
|family=Xeon Gold
|series=5000
|locked=Yes
|frequency=2,200 MHz
|turbo frequency1=3,200 MHz
|clock multiplier=22
|isa=x86-64
|isa family=x86
|microarch=Skylake
|platform=Purley
|chipset=Lewisburg
|core name=Skylake SP
|core family=6
|core stepping=M0
|process=14 nm
|technology=CMOS
|word size=64 bit
|core count=14
|thread count=28
|max cpus=4
|max memory=768 GiB
|tdp=105 W
|tcase min=0 °C
|tcase max=81 °C
|package module 1={{packages/intel/fclga-3647}}
}}
'''Xeon Gold 5120''' is a {{arch|64}} [[tetradeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5120, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.2 GHz with a TDP of 105 W and a {{intel|turbo boost}} frequency of up to 3.2 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.

== Cache ==
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
{{cache size
|l1 cache=896 KiB
|l1i cache=448 KiB
|l1i break=14x32 KiB
|l1i desc=8-way set associative
|l1d cache=448 KiB
|l1d break=14x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=14 MiB
|l2 break=14x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=19.25 MiB
|l3 break=14x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2400
|ecc=Yes
|max mem=768 GiB
|controllers=2
|channels=6
|max bandwidth=107.3 GiB/s
|bandwidth schan=17.88 GiB/s
|bandwidth dchan=35.76 GiB/s
|bandwidth qchan=71.53 GiB/s
|bandwidth hchan=107.3 GiB/s
}}

== Expansions ==
{{expansions
| pcie revision      = 3.0
| pcie lanes         = 48
| pcie config        = x16
| pcie config 2      = x8
| pcie config 3      = x4
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5120 - Intel +, Xeon Gold 5120 - Intel +, Xeon Gold 5120 - Intel +, Xeon Gold 5120 - Intel +, Xeon Gold 5120 - Intel +, Xeon Gold 5120 - Intel +, Xeon Gold 5120 - Intel +, Xeon Gold 5120 - Intel + and Xeon Gold 5120 - Intel#io +
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
chipset	Lewisburg +
clock multiplier	22 +
core count	14 +
core family	6 +
core name	Skylake SP +
core stepping	M0 +
cpuid	0x50654 +
designer	Intel +
family	Xeon Gold +
first announced	July 11, 2017 +
first launched	July 11, 2017 +
full page name	intel/xeon gold/5120 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Transactional Synchronization Extensions +, Extended Page Tables + and Advanced Vector Extensions 512 +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	896 KiB (917,504 B, 0.875 MiB) +
l1d$ description	8-way set associative +
l1d$ size	448 KiB (458,752 B, 0.438 MiB) +
l1i$ description	8-way set associative +
l1i$ size	448 KiB (458,752 B, 0.438 MiB) +
l2$ description	16-way set associative +
l2$ size	14 MiB (14,336 KiB, 14,680,064 B, 0.0137 GiB) +
l3$ description	11-way set associative +
l3$ size	19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) +
ldate	July 11, 2017 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	354.15 K (81 °C, 177.8 °F, 637.47 °R) +
max cpu count	4 +
max dts temperature	92 °C +
max memory	786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth	107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Skylake (server) +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature	0 °C +
model number	5120 +
name	Xeon Gold 5120 +
package	FCLGA-3647 +
part number	CD8067303535900 + and BX806735120 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,555.00 (€ 1,399.50, £ 1,259.55, ¥ 160,678.15) +
s-spec	SR3GD +
s-spec (qs)	QMXJ +
series	5100 +
smp interconnect	UPI +
smp interconnect links	3 +
smp interconnect rate	10.4 GT/s +
smp max ways	4 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2400 +
tdp	105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technology	CMOS +
thread count	28 +
turbo frequency (1 core)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +