Editing intel/xeon silver/4116t

{{intel title|Xeon Silver 4116T}}
{{mpu
|name=Xeon Silver 4116T
|image=skylake sp (basic).png
|designer=Intel
|manufacturer=Intel
|model number=4116T
|part number=Server
|market=Server
|first announced=July 11, 2017
|first launched=July 11, 2017
|family=Xeon Silver
|series=4000
|locked=Yes
|frequency=2,100 MHz
|turbo frequency1=3,000 MHz
|clock multiplier=21
|isa=x86-64
|isa family=x86
|microarch=Skylake
|platform=Purley
|chipset=Lewisburg
|core name=Skylake SP
|core family=6
|process=14 nm
|technology=CMOS
|word size=64 bit
|core count=12
|thread count=24
|max cpus=2
|max memory=768 GiB
|tdp=85 W
|package module 1={{packages/intel/fclga-3647}}
}}
'''Xeon Silver 4116T''' is a {{arch|64}} [[dodeca-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4116T, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.

== Cache ==
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
{{cache size
|l1 cache=768 KiB
|l1i cache=384 KiB
|l1i break=12x32 KiB
|l1i desc=8-way set associative
|l1d cache=384 KiB
|l1d break=12x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=12 MiB
|l2 break=12x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=16.5 MiB
|l3 break=12x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2400
|ecc=Yes
|max mem=768 GiB
|controllers=2
|channels=6
|max bandwidth=107.3 GiB/s
|bandwidth schan=17.88 GiB/s
|bandwidth dchan=35.76 GiB/s
|bandwidth qchan=71.53 GiB/s
|bandwidth hchan=107.3 GiB/s
}}

== Expansions ==
{{expansions
| pcie revision      = 3.0
| pcie lanes         = 48
| pcie config        = x16
| pcie config 2      = x8
| pcie config 2      = x4
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Silver 4116T - Intel#io +
base frequency	2,100 MHz (2.1 GHz, 2,100,000 kHz) +
chipset	Lewisburg +
clock multiplier	21 +
core count	12 +
core family	6 +
core name	Skylake SP +
core stepping	M0 +
designer	Intel +
family	Xeon Silver +
first announced	July 11, 2017 +
first launched	July 11, 2017 +
full page name	intel/xeon silver/4116t +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Transactional Synchronization Extensions +, Extended Page Tables + and Advanced Vector Extensions 512 +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	768 KiB (786,432 B, 0.75 MiB) +
l1d$ description	8-way set associative +
l1d$ size	384 KiB (393,216 B, 0.375 MiB) +
l1i$ description	8-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	16-way set associative +
l2$ size	12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description	11-way set associative +
l3$ size	16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldate	July 11, 2017 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	349.15 K (76 °C, 168.8 °F, 628.47 °R) +
max cpu count	2 +
max memory	786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth	107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Skylake (server) +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	4116T +
name	Xeon Silver 4116T +
package	FCLGA-3647 +
part number	CD8067303645400 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
s-spec	SR3MQ +
s-spec (qs)	QN7B +
series	4000 +
smp interconnect	UPI +
smp interconnect links	2 +
smp interconnect rate	9.6 GT/s +
smp max ways	2 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2400 +
tdp	85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technology	CMOS +
thread count	24 +
turbo frequency (1 core)	3,000 MHz (3 GHz, 3,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +