Editing acorn/microarchitectures/arm2

{{armh title|ARM2|arch}}
{{microarchitecture
|atype=CPU
|name=ARM2
|designer=ARM Holdings
|manufacturer=VLSI Technology
|manufacturer 2=Sanyo
|introduction=1986
|process=2 µm
|cores=1
|type=Scalar
|type 2=Pipelined
|stages=3
|decode=1-way
|isa=ARMv2
|l1i=0 KiB
|l1i per=Core
|l1d=0 KiB
|l1d per=Core
|predecessor=ARM1
|predecessor link=arm holdings/microarchitectures/arm1
|successor=ARM3
|successor link=arm holdings/microarchitectures/arm3



}}
'''ARM2''' is the second [[ARM]] implementation designed by [[ARM Holdings]] (then [[Acorn Computers]]) as a successor to the {{\\|ARM1}}. Introduced in 1986, the ARM2 brings a number of major improvements over its predecessor.

== Overview ==
{{see also|arm/history|l1=ARM's History}}
Introduced in 1986, the ARM2 is a reimplementation of the {{\\|ARM1}} on a smaller process along with the addition of a number of additional enhancements. The ARM2 was capable of exceeding 10 MIPS when not bottlenecked by memory with an average of around 6 MIPS. Unlike the ARM1 which was predominantly a research project, the ARM2 became the first commercially successful ARM microprocessor.

The ARM2 was designed to work as an embedded controller or a coprocessor or as a stand-alone microprocessor system. The [[Acorn Archimedes]] family of personal computers was built using the ARM2 along with a number of fully custom support chips that were also designed by Acorn Computer.

== Process Technology ==
{{see also|2 µm process}}
ARM2 chips were manufactured by [[VLSI Technology]] and [[Sanyo]] on a [[2 µm]] double-level metal [[CMOS]] process.

== Architecture ==

=== Key changes from {{\\|ARM1}} ===
* [[2 µm process]] (from [[3 µm]])
* > 2x MIPS when not bottlenecked by memory
* 27-entry register file (from 25)
** 2 new program status registers
** Aid Fast Interrupts
* New support for coprocessors
* New support for hardware multiply and accumulate

==== New instructions ====
ARM2 introduces a number of new instructions to deal with the new features:

'''Coprocessor:'''

* <code>CDP</code> - Coprocessor data process
* <code>LDC</code> - Load to coprocessor
* <code>STC</code> - Store from coprocessor
* <code>MCR</code> - Move to coprocessor
* <code>MRC</code> - Move from coprocessor

'''Arithmetics:'''
* <code>MUL</code> - Multiplication
* <code>MLA</code> - Multiplication and accumulate

=== Block Diagram ===
==== Core ====
[[File:arm2 block diagram.svg|750px]]

== Core ==
=== Pipeline ===
{{empty section}}

== Die ==
* [[2 µm process]]
* 27,000 [[transistors]]
* ~5.5 mm x 5.5 mm
* 30.25 mm² die size

== All ARM2 Chips ==
{{empty section}}

== References ==
* Furber, S. B., and A. R. Wilson. "The Acorn RISC Machine ߞ an architectural view." Electronics and Power 33.6 (1987): 402-405.
codename	ARM2 +
core count	1 +
designer	Acorn Computers +
first launched	1986 +
full page name	acorn/microarchitectures/arm2 +
instance of	microarchitecture +
instruction set architecture	ARMv2 +
manufacturer	VLSI Technology + and Sanyo +
microarchitecture type	CPU +
name	ARM2 +
pipeline stages	3 +
process	2,000 nm (2 μm, 0.002 mm) +