Editing amd/epyc/7551

{{amd title|EPYC 7551}}
{{mpu
|future=Yes
|name=EPYC 7551
|no image=Yes
|designer=AMD
|manufacturer=GlobalFoundries
|model number=7551
|market=Server
|first announced=June 20, 2017
|family=EPYC
|series=7000
|locked=No
|frequency=2,000 MHz
|turbo frequency1=3,000 MHz
|turbo frequency2=3,000 MHz
|turbo frequency3=3,000 MHz
|turbo frequency4=3,000 MHz
|turbo frequency5=3,000 MHz
|turbo frequency6=3,000 MHz
|turbo frequency7=3,000 MHz
|turbo frequency8=3,000 MHz
|turbo frequency9=3,000 MHz
|turbo frequency10=3,000 MHz
|turbo frequency11=3,000 MHz
|turbo frequency12=3,000 MHz
|turbo frequency13=2,550 MHz
|turbo frequency14=2,550 MHz
|turbo frequency15=2,550 MHz
|turbo frequency16=2,550 MHz
|turbo frequency17=2,550 MHz
|turbo frequency18=2,550 MHz
|turbo frequency19=2,550 MHz
|turbo frequency20=2,550 MHz
|turbo frequency21=2,550 MHz
|turbo frequency22=2,550 MHz
|turbo frequency23=2,550 MHz
|turbo frequency24=2,550 MHz
|turbo frequency25=2,550 MHz
|turbo frequency26=2,550 MHz
|turbo frequency27=2,550 MHz
|turbo frequency28=2,550 MHz
|turbo frequency29=2,550 MHz
|turbo frequency30=2,550 MHz
|turbo frequency31=2,550 MHz
|turbo frequency32=2,550 MHz
|bus links=4
|bus rate=8 GT/s
|clock multiplier=20
|isa=x86-64
|isa family=x86
|microarch=Zen
|core name=Naples
|core family=23
|core model=1
|core stepping=2
|process=14 nm
|transistors=19,200,000,000
|technology=CMOS
|die area=195.228 mm²
|die length=8.87 mm
|die width=22.01 mm
|mcp=Yes
|die count=4
|word size=64 bit
|core count=32
|thread count=64
|max cpus=2
|max memory=2 TiB
|tdp=180 W
|package module 1={{packages/amd/socket sp3}}
}}
'''EPYC 7551''' is a dual-socket {{arch|64}} [[32-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7551 has a base frequency of 2 GHz with a turbo frequency of 3 GHz for up to 12 active cores. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket.


{{unknown features}}

== Cache ==
{{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}}
{{cache size
|l1 cache=3 MiB
|l1i cache=2 MiB
|l1i break=32x64 KiB
|l1i desc=4-way set associative
|l1d cache=1 MiB
|l1d break=32x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=16 MiB
|l2 break=32x512 KiB
|l2 desc=8-way set associative
|l2 policy=write-back
|l3 cache=64 MiB
|l3 break=8x8 MiB
|l3 desc=16-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2666
|ecc=Yes
|max mem=2 TiB
|controllers=4
|channels=8
|max bandwidth=158.95 GiB/s
|bandwidth schan=19.89 GiB/s
|bandwidth dchan=39.72 GiB/s
|bandwidth qchan=79.47 GiB/s
|bandwidth ochan=158.95 GiB/s
|bandwidth hchan=119.21 GiB/s
}}

== Expansions ==
The EPYC 7551 has 128 Gen 3 PCIe lanes.
{{expansions
| pcie revision      = 3.0
| pcie lanes         = 128
| pcie config        = 8x16
| pcie config 2      = 32x4
| sata revision      = 
| sata ports         = 
| usb revision       = 
| usb revision 2     = 
| usb ports          = 
| usb rate           = 
| uart               = 
| uart ports         = 
| gp io              = 
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=Yes
|avx=Yes
|avx2=Yes
|avx512=No
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=Yes
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|tbt1=No
|tbt2=No
|tbmt3=No
|bpt=No
|eist=No
|sst=No
|flex=No
|fastmem=No
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=No
|txt=No
|ht=No
|vpro=No
|vtx=No
|vtd=No
|ept=No
|mpx=No
|sgx=No
|securekey=No
|osguard=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=Yes
|amdv=Yes
|rvi=No
|smt=Yes
|sensemi=Yes
|xfr=No
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	EPYC 7551 - AMD#io +
base frequency	2,000 MHz (2 GHz, 2,000,000 kHz) +
clock multiplier	20 +
core count	32 +
core family	23 +
core model	1 +
core name	Naples +
core stepping	B2 +
designer	AMD +
die area	213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
die count	4 +
family	EPYC +
first announced	June 20, 2017 +
first launched	June 20, 2017 +
full page name	amd/epyc/7551 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd secure encrypted virtualization technology	true +
has amd secure memory encryption technology	true +
has amd sensemi technology	true +
has amd transparent secure memory encryption technology	true +
has ecc memory support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multiplier	false +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	3,072 KiB (3,145,728 B, 3 MiB) +
l1d$ description	8-way set associative +
l1d$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ description	4-way set associative +
l1i$ size	2,048 KiB (2,097,152 B, 2 MiB) +
l2$ description	8-way set associative +
l2$ size	16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
l3$ description	16-way set associative +
l3$ size	64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldate	June 20, 2017 +
manufacturer	GlobalFoundries +
market segment	Server +
max case temperature	354.15 K (81 °C, 177.8 °F, 637.47 °R) +
max cpu count	2 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth	158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) +
max memory channels	8 +
max pcie lanes	128 +
microarchitecture	Zen +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	7551 +
name	EPYC 7551 +
package	FCLGA-4094 + and SP3 +
part number	PS7551BDVIHAF +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 3,400.00 (€ 3,060.00, £ 2,754.00, ¥ 351,322.00) +
series	7001 +
smp max ways	2 +
socket	SP3 + and LGA-4094 +
supported memory type	DDR4-2666 +
tdp	180 W (180,000 mW, 0.241 hp, 0.18 kW) +
technology	CMOS +
thread count	64 +
transistor count	19,200,000,000 +
turbo frequency (10 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (11 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (12 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (13 cores)	2,550 MHz (2.55 GHz, 2,550,000 kHz) +
turbo frequency (14 cores)	2,550 MHz (2.55 GHz, 2,550,000 kHz) +
turbo frequency (15 cores)	2,550 MHz (2.55 GHz, 2,550,000 kHz) +
turbo frequency (16 cores)	2,550 MHz (2.55 GHz, 2,550,000 kHz) +
turbo frequency (17 cores)	2,550 MHz +
turbo frequency (18 cores)	2,550 MHz +
turbo frequency (19 cores)	2,550 MHz +
turbo frequency (1 core)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (20 cores)	2,550 MHz +
turbo frequency (21 cores)	2,550 MHz +
turbo frequency (22 cores)	2,550 MHz +
turbo frequency (23 cores)	2,550 MHz +
turbo frequency (24 cores)	2,550 MHz +
turbo frequency (25 cores)	2,550 MHz +
turbo frequency (26 cores)	2,550 MHz +
turbo frequency (27 cores)	2,550 MHz +
turbo frequency (28 cores)	2,550 MHz +
turbo frequency (29 cores)	2,550 MHz +
turbo frequency (2 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (30 cores)	2,550 MHz +
turbo frequency (31 cores)	2,550 MHz +
turbo frequency (32 cores)	2,550 MHz +
turbo frequency (3 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (4 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (5 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (6 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (7 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (8 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (9 cores)	3,000 MHz (3 GHz, 3,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +