Editing intel/microarchitectures/kaby lake

{{intel title|Kaby Lake|arch}}
{{microarchitecture
| atype            = CPU
| name             = Kaby Lake
| designer         = Intel
| manufacturer     = Intel
| introduction     = August 30, 2016
| phase-out        = 
| process          = 14 nm
| cores            = 2
| cores 2          = 4<!-- those should come in due time
| cores 3          = 6
| cores 4          = 8
| cores 5          = 10
| cores 6          = 12
| cores 7          = 14
| cores 8          = 16
| cores 9          = 18
| cores 10         = 20
| cores 11         = 22-->

| pipeline         = Yes
| type             = Superscalar
| OoOE             = Yes
| speculative      = Yes
| renaming         = Yes
| isa              = IA-32
| isa 2            = x86-64
| stages min       = 14
| stages max       = 19
| issues           = 5

| inst             = Yes
| feature          = 
| extension        = MOVBE
| extension 2      = MMX
| extension 3      = SSE
| extension 4      = SSE2
| extension 5      = SSE3
| extension 6      = SSSE3
| extension 7      = SSE4.1
| extension 8      = SSE4.2
| extension 9      = POPCNT
| extension 10     = AVX
| extension 11     = AVX2
| extension 12     = AES
| extension 13     = PCLMUL
| extension 14     = FSGSBASE
| extension 15     = RDRND
| extension 16     = FMA3
| extension 17     = F16C
| extension 18     = BMI
| extension 19     = BMI2
| extension 20     = VT-x
| extension 21     = VT-d
| extension 22     = TXT
| extension 23     = TSX
| extension 24     = RDSEED
| extension 25     = ADCX
| extension 26     = PREFETCHW
| extension 27     = CLFLUSHOPT
| extension 28     = XSAVE
| extension 29     = SGX
| extension 30     = MPX
| extension 31     = AVX-512

| cache            = Yes
| l1i              = 32 KiB
| l1i per          = core
| l1i desc         = 8-way set associative
| l1d              = 32 KiB
| l1d per          = core
| l1d desc         = 8-way set associative
| l2               = 256 KiB
| l2 per           = core
| l2 desc          = 4-way set associative
| l3               = 2 MiB
| l3 per           = core
| l3 desc          = Up to 16-way set associative
| l4               = 64 MiB
| l4 per           = package
| l4 desc          = on Iris Plus GPUs only

| core names       = Yes
| core name        = Kaby Lake Y
| core name 2      = Kaby Lake U
| core name 3      = Kaby Lake H
| core name 4      = Kaby Lake S
| core name 5      = Kaby Lake X
| core name 6      = Kaby Lake DT

| succession       = Yes
| predecessor      = Skylake
| predecessor link = intel/microarchitectures/skylake
| successor        = Coffee Lake
| successor link   = intel/microarchitectures/coffee lake
| successor 2      = Cannonlake
| successor 2 link = intel/microarchitectures/cannonlake
}}
[[File:7th Gen Core-i7-badge.png|thumb|right|250px|Kaby Lake is Intel's 7th Generation {{intel|Core i7}} MPUs.]]
'''Kaby Lake''' ('''KBL''') is [[Intel]]'s successor to {{\\|Skylake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops, servers, and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. {{\\|Cannonlake}} was originally set to replace {{\\|Skylake}} as the next microarchitecture using a [[10 nm process]], however Intel later revised their roadmap to include Kaby Lake (with Cannonlake being pushed back to [[2017]]). 

For desktop and mobile, Kaby Lake is branded as 7th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. For server class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v6}}, {{intel|Xeon E5|Xeon E5 v6}}, and {{intel|Xeon E7|Xeon E7 v6}}.

== Codenames ==
{| class="wikitable"
|-
! Core !! Abbrev !! Description !! Graphics !! Target
|-
| {{intel|Kaby Lake Y|l=core}} || KBL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks
|-
| {{intel|Kaby Lake U|l=core}} || KBL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
|-
| {{intel|Kaby Lake H|l=core}} || KBL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations
|-
| {{intel|Kaby Lake S|l=core}} || KBL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis
|-
| {{intel|Kaby Lake R|l=core}} || KBL-R || ||  || Kaby Lake U Refresh?
|-
| {{intel|Kaby Lake G|l=core}} || KBL-G || ||  || Kaby Lake + ?
|-
| {{intel|Kaby Lake X|l=core}} || KBL-X || Extreme Performance || || High-end desktops & enthusiasts market
|-
| {{intel|Kaby Lake DT|l=core}} || KBL-DT || Workstation || GT2 || Workstations & entry-level servers
|}

== Brands ==
Intel released Kaby Lake under 6 main brand families:

{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
|-
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features
|-
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
|-
| [[File:intel celeron (2015).png|50px]] || {{intel|Celeron}} || style="text-align: left;" | Entry-level Budget || [[dual-core|dual]] || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘
|-
| rowspan="2" | [[File:intel pentium (2015).png|50px]] || rowspan="2" | {{intel|Pentium (2009)|Pentium}} || style="text-align: left;" | Budget (Mobile) || rowspan="2" | dual || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘
|-
| style="text-align: left;" | Budget (Desktop) || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #d6ffd8;" | ✔
|-
| rowspan="2" | [[File:core i3 logo (2015).png|50px]] || rowspan="2" |  {{intel|Core i3}} || style="text-align: left;" | Low-end Performance || rowspan="2" |  dual || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘
|-
| style="text-align: left;" | Low-end Performance (E Series) || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ || style="background-color: #d6ffd8;" | ✔
|-
| rowspan="2" | [[File:core i5 logo (2015).png|50px]] || rowspan="2" | {{intel|Core i5}} || rowspan="2" style="text-align: left;" | Mid-range Performance || dual || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘
|-
|[[quad-core|quad]] || style="background-color: #ffdad6;" | ✘ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘
|-
| rowspan="2" | [[File:core i7 logo (2015).png|50px]] || rowspan="2" | {{intel|Core i7}} || rowspan="2" style="text-align: left;" | High-end Performance || dual || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘
|-
|quad || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘
|-
| [[File:xeon logo (2015).png|50px]] ||  {{intel|Xeon E3}} || style="text-align: left;" | Workstation high-performance/dense servers || quad || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ 
|}

== Release Dates ==
Kaby Lake is set to be released in two phases. The first phase was announced in August of [[2016]] and was primarily aimed at various low-power consumer products such as light notebooks and 2-in-1s. Those devices are powered by {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|l=core}} CPUs. Intel released mainstream {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|l=core}} processors on January 3, [[2017]] in time for CES 2017. Additionally, {{intel|Kaby Lake X|l=core}} are expecting to be released in late August during Gamescom 2017.

== Process Technology ==
{| class="wikitable" style="float: right;"
! colspan="2" | 14 nm Manufacturing Fabs
|-
! Fab !! Location
|-
| D1X || Hillsboro, Oregon
|-
| D1D || Hillsboro, Oregon
|-
| D1C || Hillsboro, Oregon
|-
| Fab 32 || Chandler, Arizona
|-
| Fab 24 || Leixlip, Ireland
|}
{{see also|intel/microarchitectures/broadwell#Process_Technology|l1=Broadwell § Process Technology}}
Kaby Lake uses a modified and improved [[14 nm process]] used for the Broadwell microarchitecture (And {{\\|Skylake}}). Intel calls the modified process "14nm+". The new process has improved [[transistor]] channel strain. The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). These changes allowed Intel to increase the maximum frequencies of all models by around 100 to 300 [[megahertz]] which gives many [[single-thread]] applications a modest performance increase. Overall transistors improvement allowed for +12% drive current.

[[File:intel 14nm+ (nmos).png|400px]]
[[File:intel 14nm+ (pmos).png|400px]]

== Compatibility ==
There are no official drivers by Intel for [[Windows 7]] or [[Windows 8]]. Microsoft announced that only [[Windows 10]] will have support for Kaby Lake. [[Linux]] added initial support for Kaby Lake starting with Linux Kernel 4.5.

{| class="wikitable"
! Vendor !! OS  !! Version !! Notes
|-
| rowspan="3" | Microsoft || rowspan="3" | Windows || style="background-color: #ffdad6;" | Windows 7 || No Support
|-
| style="background-color: #ffdad6;" | Windows 8 || No Support
|-
| style="background-color: #d6ffd8;" | Windows 10 || Support
|- 
| Linux || Linux || style="background-color: #d6ffd8;" | Kernel 4.5 || Initial Support (Fedora 24, Yocto v2.2, ..)
|-
| Google || Chromium || style="background-color: #d6ffd8;" | Chromium || Support
|-
| Wind River || VxWorks || style="background-color: #d6ffd8;" | VxWorks 7 || Support
|}

== Compiler support ==
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable
|-
| [[ICC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[GCC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[LLVM]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code>
|}

== Architecture ==
{{see also|intel/microarchitectures/skylake#Key_changes_from_Broadwell|l1=Skylake § Key changes from Broadwell}}
[[File:kaby lake silicon wafer.jpg|right|thumb|Kaby Lake silicon [[wafer]] with 7th generation core processor dies.]]
While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of enhancements in Kaby Lake. Note that because of the improvements done to the process and the uplift in binning, it is the mostly the ultra-low power (i.e. mobile) processors that will see the most substantial gain. Likewise, the high-end models will see very little gain. 

=== Key changes from {{\\|Skylake}} ===
* Same IPC as Skylake (i.e. performance/[[MHz]] is unchanged)
* Enhanced "14nm+" process results in ~15% higher frequency (100 to 300 MHz increase across the board)
* 10x performance/[[Watt]] over {{\\|Nehalem}} (Up from 8x)
* {{intel|LGA-1151|Socket 1151}} now uses {{intel|Union Point}} (200-series chipset) (See [[#Sockets.2FPlatform|§ Sockets]])
* [[intel/microarchitectures/skylake#.22Speed_Shift.22_.28new_power_management.29|SkyLake's Speed Shift]] implementation is significantly improved, cutting responsiveness by as much as 66% (down to just ~10-15ms to peak frequency).
* Support for {{intel|Optane}} Technology

* Interfaces
** [[Embedded DisplayPort]] ([[eDP]]) now supports eDP Standard 1.4 (From 1.3 in Skylake)

* {{intel|Gen 9.5|l=arch}} GPUs
** New native hardware support for 4K HEVC/VP9 (See [[#Graphics|§ Graphics]])
** {{intel|HD Graphics 510}} '''→''' {{intel|HD Graphics 610}} (12 Execution Units, no change)
** {{intel|HD Graphics 515}} '''→''' {{intel|HD Graphics 615}} (24 Execution Units, no change)
** {{intel|HD Graphics 520}} '''→''' {{intel|HD Graphics 620}} (24 Execution Units, no change)
** {{intel|HD Graphics 530}} '''→''' {{intel|HD Graphics 630}} (24 Execution Units, no change)
** {{intel|HD Graphics P530}} '''→''' {{intel|HD Graphics P630}} (24 Execution Units, no change)
** {{intel|Iris Graphics 540}} '''→''' {{intel|Iris Plus Graphics 640}} (48 Execution Units, no change)
** {{intel|Iris Graphics 550}} '''→''' {{intel|Iris Plus Graphics 650}} (48 Execution Units, no change)

* Families
** {{intel|Core i3}} processors dropped support for ECC memory (except for Embedded models)
** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.)

=== Block Diagram ===
==== Entire SoC Overview ====
[[File:kaby lake soc block diagram.svg|900px]]

==== Individual Core ====
[[File:skylake block diagram.svg]]

==== Gen9.5 ====
See {{intel|Gen9.5#Gen9.5|l=arch}}.

=== Memory Hierarchy ===
The overall memory structure is identical to {{\\|Skylake}}.
* Cache
** L1I Cache:
*** 32 KiB 8-way set associative
**** 64 B line size
**** shared by the two threads, per core
** L1D Cache:
*** 32 KiB 8-way set associative
*** 64 B line size
*** shared by the two threads, per core
*** 4 cycles for fastest load-to-use
*** 64 Bytes/cycle load bandwidth
*** 32 Bytes/cycle store bandwidth
*** Write-back policy
** L2 Cache:
*** unified, 256 KiB 4-way set associative
*** 12 cycles for fastest load-to-use
*** 64B/cycle bandwidth to L1$
*** Write-back policy
** L3 Cache/LLC:
*** Up to 2 MiB Per core, shared across all cores.
*** Up to 16-way set associative
*** Write-back policy
*** Per each core:
**** Read: 32 B/cycle (@ ring [[clock]])
**** Write: 32 B/cycle (@ ring clock)
** Side Cache:
*** 64 MiB [[eDRAM]]
*** Per package
*** Only on the Iris Plus GPUs
*** Read: 32B/cycle (@ [[eDRAM]] clock)
*** Write: 32B/cycle (@ EDRAM clock)
** System [[DRAM]]:
*** 2 Channels
*** 8B/cycle/channel (@ memory clock)

Kaby Lake TLB consists of dedicated level one TLB for instruction cache and another one for data cache. Additionally there is a unified second level TLB.
* TLBs:
** ITLB
*** 4 KiB page translations:
**** 128 entries; 8-way set associative
**** dynamic partition; divided between the two threads
*** 2 MiB / 4 MiB page translations:
**** 8 entries; fully associative
**** Duplicated for each thread
** DTLB
*** 4 KiB page translations:
**** 64 entries; 4-way set associative
**** fixed partition; divided between the two threads
*** 2 MiB / 4 MiB page translations:
**** 32 entries; 4-way set associative
**** fixed partition
*** 1G page translations:
**** 4 entries; 4-way set associative
**** fixed partition
** STLB
*** 4 KiB + 2 MiB page translations:
**** 1536 entries; 12-way set associative
**** fixed partition
*** 1 GiB page translations:
**** 16 entries; 4-way set associative
**** fixed partition

=== Pipeline ===
{{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake §Pipeline}}
Kaby Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}.

==== Execution engine ====
Kaby Lake execution engine should be very similar to {{\\|Skylake}}. No big changes are known to have taken place.

{| class="wikitable" style="text-align: center;"
|-
! colspan="8" | Dispatch Ports
|-
! Port 0 !! Port 1 !! Port 2 !! Port 3 !! Port 4 !! Port 5 !! Port 6 !! Port 7
|-
| ALU<br>Vec ALU || ALU<br>Fast LEA<br>Vec ALU || Load Addr<br>Store Addr || Load Addr<br>Store Addr || Store Data || ALU<br>Fast LEA<br>Vec ALU || ALU<br>Shift || Store Addr
|-
| Vec Shift<br>Vec Add || Vec Shift<br>Vec Add || || || || Vec Shuffle || Branch ||
|-
| Vec Mul<br>FMA || Vec Mul<br>FMA || || || || || ||
|-
| DIV || Slow Int || || || || || ||
|-
| Branch2 || Slow LEA || || || || || ||
|}

==== Execution Units ====

{| class="wikitable"
|-
! colspan="3" | Execution Units 
|-
! Execution Unit !! # of Units !! Instructions
|-
| ALU || 4 || add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa, (v)movap*, (v)movup*
|-
| DIV || 1 || divp*, divs*, vdiv*, sqrt*, vsqrt*, rcp*, vrcp*, rsqrt*, idiv
|-
| Shift || 2 || sal, shl, rol, adc, sarx, adcx, adox, etc...
|-
| Shuffle || 1 || (v)shufp*, vperm*, (v)pack*, (v)unpck*, (v)punpck*, (v)pshuf*, (v)pslldq, (v)alignr, (v)pmovzx*, vbroadcast*, (v)pslldq, (v)psrldq, (v)pblendw
|-
| Slow Int || 1 || mul, imul, bsr, rcl, shld, mulx, pdep, etc...
|-
| BM<info>Bit Manipulation</info> || 2 || andn, bextr, blsi, blsmsk, bzhi, etc
|-
| FP Mov || 1 || (v)movsd/ss, (v)movd gpr
|-
| SIMD Misc || 1 || STTNI, (v)pclmulqdq, (v)psadw, vector shift count in xmm
|-
| Vec ALU || 3 || (v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)movap*, (v)movup*, (v)andp*, (v)orp*, (v)paddb/w/d/q, (v)blendv*, (v)blendp*, (v)pblendd
|-
| Vec Shift || 2 || (v)psllv*, (v)psrlv*, vector shift count in imm8
|-
| Vec Add || 2 || (v)addp*, (v)cmpp*, (v)max*, (v)min*, (v)padds*, (v)paddus*, (v)psign, (v)pabs, (v)pavgb, (v)pcmpeq*, (v)pmax, (v)cvtps2dq, (v)cvtdq2ps, (v)cvtsd2si, (v)cvtss2si
|-
| Vec Mul || 2 || (v)mul*, (v)pmul*, (v)pmadd*
|}

=== Graphics ===
{{main|intel/microarchitectures/gen9.5|l1=Gen9.5}}
Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, an [[Embedded DisplayPort]] (eDP) 1.4 interfaces. Kaby Lake's biggest enhancement is the addition of native [[fixed function]] HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as [[fixed function]] HEVC/VP9 encoding for 4K (8-bit).

{| class="wikitable tc2 tc3"
|-
! colspan="5" | [[Integrated Graphics Processor]] !! colspan="9" | Standards
|-
! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !!  rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]]
|-
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
|-
| {{intel|HD Graphics 610}} || 12 || GT1 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake U|U}} || - || rowspan="7" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="7" style="text-align: center;" | '''12''' || rowspan="7" style="text-align: center;" | '''N/A''' || rowspan="7" style="text-align: center;" | '''5.1''' || rowspan="7" style="text-align: center;" | '''4.4''' || rowspan="7" style="text-align: center;" | '''4.5''' || rowspan="7" style="text-align: center;"  colspan="2" | '''2.0'''
|-
| {{intel|HD Graphics 615}} || 24 || GT2|| {{intel|Kaby Lake Y|Y}} || -
|-
| {{intel|HD Graphics 620}} || 24 || GT2 || {{intel|Kaby Lake U|U}} || -
|-
| {{intel|HD Graphics 630}} || 24 || GT2 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake H|H}} || -
|-
| {{intel|HD Graphics P630}} || 24 || GT2 || {{intel|Kaby Lake H|H}} || -
|-
| {{intel|Iris Plus Graphics 640}} || 48 || GT3e|| {{intel|Kaby Lake U|U}} || 64 MiB
|-
| {{intel|Iris Plus Graphics 650}} || 48 || GT3e || {{intel|Kaby Lake U|U}} || 64 MiB
|}

<references group=graphics />
==== Hardware Accelerated Video ====
{{kaby lake hardware accelerated video table}}

=== Sockets/Platform ===
{{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|U|l=core}} are single-chip solutions. {{intel|Kaby Lake Y|Y|l=core}} chips utilize a 2-die [[multi-chip package]] (MCP) whereas the {{intel|Kaby Lake U|l=core}}'s are either 2 or 3-die MCP configuration. The 3 dice chip configuration are for the Iris [[IGP]]s which incorporate an on-package cache (OPC) in addition to the hub. Communication from the CPU to the hub on those chips are done via a lightweight On-Package Interconnect (OPI) interface. {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|H|l=core}} are a two-chip solution linked together via Intel's standard [[DMI 3.0]] bus interface which utilizes 4 of the CPU's 20 [[PCIe]] 3.0 lanes (having a transfer rate of 8 GT/s per lane). Only {{intel|Kaby Lake S|l=core}} (used on mainstream desktop processors) are not soldered onto the [[motherboard]] and can be interchanged/replaced.
{| class="wikitable" style="text-align: center;"
|-
! !! Core !! Socket !! Permanent !! Platform !! Chipset !! Bus
|-
| [[File:kaby lake y (back).png|100px|link=intel/cores/kaby_lake_y]] || {{intel|Kaby Lake Y|l=core}} || {{intel|BGA-1515}} || Yes || 1-chip || rowspan="2" | N/A || rowspan="2" | OPI
|-
| [[File:kaby lake u (back; standard).png|100px|link=intel/cores/kaby_lake_u]] || {{intel|Kaby Lake U|l=core}} || {{intel|BGA-1356}} || Yes || 1-chip
|-
| [[File:kaby lake h (back).png|100px|link=intel/cores/kaby_lake_h]] || {{intel|Kaby Lake H|l=core}} || {{intel|BGA-1440}} || Yes || 2-chip || rowspan="2" | {{intel|Sunrise Point}}<ref group="c">Requires a firmware update in order to work with Kaby Lake chips</ref><br>{{intel|Union Point}} || rowspan="4" | [[DMI 3.0]]
|-
| rowspan="2" | [[File:kaby lake s (back).png|100px|link=intel/cores/kaby_lake_s]] || {{intel|Kaby Lake S|l=core}} || {{intel|LGA-1151}} || No || 2-chip 
|-
| {{intel|Kaby Lake DT|l=core}} || {{intel|LGA-1151}} || No || 2-chip || Xeon {{intel|Sunrise Point}}<br>Xeon {{intel|Union Point}}
|-
| &nbsp; || {{intel|Kaby Lake X|l=core}} || {{intel|LGA-2066}} || No || 2-chip || {{intel|Lewisburg}}
|}

<references group="c" />

== Clock domains ==
Kaby Lake is divided into a number of [[clock domains]], each controlling the clock frequency of their respective unit in the processor. All clock domains are some multiple of the [virtual] bus clock ([[BCLK]]).

* '''BCLK''' - Bus Clock - The  system bus interface frequency (once upon a time referred to the actual [[FSB]] speed, it now serves as only a base clock reference for all other clock domains). The bus clock is 100 MHz.
* '''Core Clock''' - The frequency at which the core and the [[L1]]/[[L2]] caches operate at. (Frequency depends on the model and is represented as a multiple of BCLK).
* '''Ring Clock''' - The frequency at which the ring interconnect and [[L3$|LLC]] operate at. Data from/to the individual cores are read/written into the L3 at a rate of 32B/cycle operating at Ring Clock frequency.
* '''IGP Clock''' - The frequency at which the [[integrated graphics]] ({{\\|Gen9}} GPU) operates at. Data from/to the GPU are read/written into the LLC at a rate of 64B/cycle operating at this frequency as well.
* '''eDRAM Clock''' - The frequency at which the [[embedded DRAM]] operates at (only available for certain models). Data is read/written from/to the LLC at a rate of 32B/cycle operating at this frequency as well.
* '''MemClk''' - Memory Clock - The frequency at which the system DRAM operates at. DRAM data is transfered at a rate of 8B/cycle operating at MemClk frequency.

[[File:kaby lake soc clock domain block diagram.svg|850px]]

== Die ==
Kaby Lake desktop and mobile come and [[2 cores|2]] and [[4 cores|4]] cores. Each variant has its own die. One of the most noticeable changes on die is the amount of die space allocated to the [[GPU]]. The major components of the die is:

* System Agent
* CPU Core
* Ring bus interconnect
* Memory Controller

=== System Agent ===
The System Agent (SA) contains the Image Processing Unit (IPU), the Display Engine (DE), and the I/O bus. Note that the mainstream desktop (i.e., [[quad-core]] die) does not have an IPU (The memory controller actually occupies a portion of where it would otherwise be).

<div>
<div style="float: left;  margin: 10px;">[[File:kaby lake 2c sa.png|100px]]</div>
<div style="float: left;  margin: 10px;">[[File:kaby lake 2c sa (annotated).png|100px]]</div>
</div> 

{{clear}}

=== Dual-Core ===
Die shot of the [[dual-core]] {{intel|Kaby Lake S|l=core}} (Desktop) processors:

: [[File:kaby lake (dual core).png|850px]]


: [[File:kaby lake (dual core) (annotated).png|850px]]

=== Quad-Core ===
Die shot of the [[quad-core]] {{intel|Kaby Lake S|l=core}} (Desktop) processors:

: [[File:kaby lake (quad core).png|850px]]


: [[File:kaby lake (quad core) (annotated).png|850px]]

== All Kaby Lake Chips ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="25">Kaby Lake Chips</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="13">Main processor</th><th colspan="3">IGP</th><th colspan="9">Major Feature Diff</th></tr>
<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th>Platform</th><th>Core</th><th data-sort-type="number">C</th><th data-sort-type="number">T</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>[[ECC]]</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr>
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Uniprocessors]]</th></tr>
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?platform
 |?core name
 |?core count
 |?thread count
 |?l3$ size
 |?l4$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |?has_ecc_memory_support
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |?has advanced vector extensions
 |?has advanced vector extensions 2
 |?has intel trusted execution technology
 |?has transactional synchronization extensions
 |?has intel vpro technology
 |?has_intel_vt-d_technology
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=27:19
 |mainlabel=-
 |limit=100
}}
{{comp table count|ask=[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Kaby Lake]]}}
</table>
{{comp table end}}

== Documents ==
* [[:File:7th-gen-intel-core-january-product-brief.pdf|7th gen intel core & Intel Xeon processor briefing]]
* [[:File:7th Generation Intel® Core™ Processor Product Brief.pdf|7th Generation Intel Core Processor Product Brief]]
* [[:File:7th-gen-intel-core-january-fact-sheet.pdf|7th Gen Intel Core & Xeon Processor Family Fact Sheet]]
* [[:File:7th-gen-intel-core-vpro-product-brief.pdf|7th Generation Intel Core vPro Processor Briefing]]
* [[:File:7th Generation Intel® Core™ Processor Y-Series and U-Series Product Brief.pdf|7th Generation Intel Core Processor Y-Series and U-Series Product Brief]]
* [[:File:7th Gen Intel® Core™ Processor Family Fact Sheet.pdf|7th Gen Intel Core Processor Family Fact Sheet]]
* [[:File:7th-generation-core-processor-deskop-iot-platform-brief.pdf|7th Generation Intel Core Processor-Based Platforms for Internet of Things (IoT) Solutions Platform brief]]
* [[:File:how-to-watch-4k-uhd-premium-content-with-your-pc.pdf|HOW TO WATCH 4K ULTRA HD (UHD) PREMIUM CONTENT WITH YOUR PC]]

== References ==
* Intel Technology and Manufacturing Day, March 28, 2017

== Artwork ==
<gallery>
File:7th Gen Intel Core i3 unlocked box.png|Kaby Lake offers the first unlocked {{intel|Core i3}} model.
File:7th Gen Intel Core i7 unlocked box - front.png
File:7th Gen Intel Core i7 unlocked box - back.png
File:7th Gen Intel Core family.jpg
File:7th Gen-Navoy-1.JPG|Navin Shenoy, Intel corporate vice president and general manager for its Client Computing Group
File:7th Gen-Navoy-2.JPG
File:7th Gen-Navoy-3.JPG
File:7th Gen-Walker-1.JPG|Chris Walker, Intel vice president for its Client Computing Group and general manager of notebook product marketing
File:7th Gen-Walker-2.JPG
File:7th Gen-Walker-3.JPG
File:7th Gen-water-1.JPG
File:7th-gen-wafer.jpg|7th gen core silicon wafers
</gallery>

== See also ==
* {{amd|microarchitectures/zen|AMD's Zen}}
codename	Kaby Lake +
core count	2 + and 4 +
designer	Intel +
first launched	August 30, 2016 +
full page name	intel/microarchitectures/kaby lake +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Kaby Lake +
pipeline stages (max)	19 +
pipeline stages (min)	14 +
process	14 nm (0.014 μm, 1.4e-5 mm) +