Editing intel/core i5/i5-520m

{{intel title|Core i5-520M}}
{{mpu
| name                = Intel Core i5-520M
| no image            = yes
| image               = 
| image size          = 
| caption             = 
| designer            = Intel
| manufacturer        = Intel
| model number        = i5-520M
| part number         = 
| market              = Mobile
| first announced     = January 7, 2010
| first launched      = January 7, 2010
| last order          = 
| last shipment       = 
| release price       = $225

| family              = Core i5
| series              = i5-500
| locked              = Yes
| frequency           = 2399.99 MHz
| turbo frequency     = Yes
| turbo frequency1    = 2,933.33 MHz
| turbo frequency2    = 2,666.66 MHz
| bus type            = DMI 1.0
| bus speed           = 
| bus rate            = 2.5 GT/s
| bus links           = 1
| clock multiplier    = 18
| s-spec              = SLBNB
| s-spec 2            = SLBNA
| s-spec 3            = SLBU3
| s-spec 4            = SLBU4
| s-spec qs           = 
| cpuid               = 0x20655

| microarch           = Westmere
| platform            = Calpella
| chipset             = Ibex Peak
| core name           = Arrandale
| core family         = 6
| core model          = 37
| core stepping       = K0
| core stepping 2     = C2
| process             = 32 nm
| transistors         = 382,000,000
| technology          = CMOS
| die area            = 81 mm²
| die width           = 
| die length          = 
| word size           = 64 bit
| core count          = 2
| thread count        = 4
| max cpus            = 1
| max memory          = 8 GiB

| electrical          = Yes
| v core              = 
| v core tolerance    = 
| v io                = 
| v io tolerance      = 
| sdp                 = 
| tdp                 = 35 W
| tjunc min           = 0 °C
| tjunc max           = 105 °C
| tcase min           = 
| tcase max           = 
| tstorage min        = -25 °C
| tstorage max        = 125 °C
| tambient min        = 
| tambient max        = 

| package module 1    = {{packages/intel/rpga-988a}}
| package module 2    = {{packages/intel/bga-1288}}
}}
'''Core i5-520M''' is a {{arch|64}} [[x86]] [[dual-core]] mobile microprocessor introduced by [[Intel]] in [[2010]]. This processor, which is based on the {{intel|Westmere|l=arch}} microarchitecture ({{intel|Arrandale|l=core}} core), is manufactured on a [[32 nm process]]. This MPU operates at a base frequency of 2.40 GHz with a {{intel|Turbo Boost}} frequency of 2.93 GHz and a TDP of 35 W. This processor incorporated the {{intel|HD Graphics (Ironlake)}} [[IGP]] on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 766.00 MHz.

== Cache ==
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}}
{{cache size
|l1 cache=128 KiB
|l1i cache=64 KiB
|l1i break=2x32 KiB
|l1i desc=4-way set associative
|l1i policy=write-back
|l1d cache=64 KiB
|l1d break=2x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=512 KiB
|l2 break=2x256 KiB
|l2 desc=8-way set associative
|l2 policy=write-back
|l3 cache=3 MiB
|l3 break=2x1.5 MiB
|l3 desc=12-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR3-1066
|ecc=No
|max mem=8 GiB
|controllers=1
|channels=2
|max bandwidth=15.88 GiB/s
|bandwidth schan=7.942 GiB/s
|bandwidth dchan=15.88 GiB/s
|pae=36 bit
}}

== Expansions ==
{{expansions
| pcie revision      = 2.0
| pcie lanes         = 16
| pcie config        = 1x16
}}

== Graphics ==
{{integrated graphics
| gpu                 = HD Graphics (Ironlake)
| device id           = 0x0046
| designer            = Intel
| execution units     = 12
| max displays        = 2
| max memory          = 
| frequency           = 500 MHz
| max frequency       = 766 MHz

| directx ver         = 10.1
| opengl ver          = 2.1

| features             = Yes
| intel quick sync     = 
| intel intru 3d       = 
| intel insider        = 
| intel widi           = 
| intel fdi            = Yes
| intel clear video    = Yes
| intel clear video hd = Yes
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Core i5-520M - Intel#package + and Core i5-520M - Intel#io +
base frequency	2,399.99 MHz (2.4 GHz, 2,399,990 kHz) +
bus links	1 +
bus rate	2,500 MT/s (2.5 GT/s, 2,500,000 kT/s) +
bus type	DMI 1.0 +
chipset	Ibex Peak +
clock multiplier	18 +
core count	2 +
core family	6 +
core model	37 +
core name	Arrandale +
core stepping	K0 + and C2 +
cpuid	0x20655 +
designer	Intel +
device id	0x0046 +
die area	81 mm² (0.126 in², 0.81 cm², 81,000,000 µm²) +
family	Core i5 +
first announced	January 7, 2010 +
first launched	January 7, 2010 +
full page name	intel/core i5/i5-520m +
has ecc memory support	false +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 1.0 +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Flex Memory Access +, Enhanced SpeedStep Technology + and Extended Page Tables +
has intel enhanced speedstep technology	true +
has intel flex memory access support	true +
has intel trusted execution technology	true +
has intel turbo boost technology 1 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	HD Graphics (Ironlake) +
integrated gpu base frequency	500 MHz (0.5 GHz, 500,000 KHz) +
integrated gpu designer	Intel +
integrated gpu execution units	12 +
integrated gpu max frequency	766 MHz (0.766 GHz, 766,000 KHz) +
isa	x86-64 +
isa family	x86 +
l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	4-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	8-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description	12-way set associative +
l3$ size	3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
last order	October 19, 2012 +
last shipment	January 18, 2013 +
ldate	January 7, 2010 +
manufacturer	Intel +
market segment	Mobile + and Embedded +
max cpu count	1 +
max junction temperature	378.15 K (105 °C, 221 °F, 680.67 °R) +
max memory	8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max memory bandwidth	15.88 GiB/s (16,261.12 MiB/s, 17.051 GB/s, 17,051.02 MB/s, 0.0155 TiB/s, 0.0171 TB/s) +
max memory channels	2 +
max pcie lanes	16 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Westmere +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	i5-520M +
name	Intel Core i5-520M +
package	rPGA-988A + and BGA-1288 +
part number	BX80617I5520M +, CN80617004119AE + and CP80617004119AE +
platform	Calpella +
process	32 nm (0.032 μm, 3.2e-5 mm) +
release price	$ 225.00 (€ 202.50, £ 182.25, ¥ 23,249.25) +
s-spec	SLBNB +, SLBNA +, SLBU3 + and SLBU4 +
series	i5-500 +
smp max ways	1 +
supported memory type	DDR3-1280 +
tdp	35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
technology	CMOS +
thread count	4 +
transistor count	382,000,000 +
turbo frequency (1 core)	2,933.33 MHz (2.933 GHz, 2,933,330 kHz) +
turbo frequency (2 cores)	2,666.66 MHz (2.667 GHz, 2,666,660 kHz) +
word size	64 bit (8 octets, 16 nibbles) +