Editing intel/core i5/i5-520um

{{intel title|Core i5-520UM}}
{{mpu
| name                = Intel Core i5-520UM
| no image            = yes
| image               = 
| image size          = 
| caption             = 
| designer            = Intel
| manufacturer        = Intel
| model number        = i5-520UM
| part number         = 
| market              = Mobile
| first announced     = January 7, 2010
| first launched      = January 7, 2010
| last order          = 
| last shipment       = 
| release price       = $241

| family              = Core i5
| series              = i5-500
| locked              = Yes
| frequency           = 1,066.66 MHz
| turbo frequency     = Yes
| turbo frequency1    = 1,866.66 MHz
| turbo frequency2    = 1,599.99 MHz
| bus type            = DMI 1.0
| bus speed           = 
| bus rate            = 2.5 GT/s
| bus links           = 1
| clock multiplier    = 8
| s-spec              = SLBQP
| s-spec 2            = SLBSQ
| s-spec qs           = 
| cpuid               = 

| microarch           = Westmere
| platform            = Calpella
| chipset             = Ibex Peak
| core name           = Arrandale
| core family         = 6
| core model          = 37
| core stepping       = K0
| core stepping 2     = C2
| process             = 32 nm
| transistors         = 382,000,000
| technology          = CMOS
| die area            = 81 mm²
| die width           = 
| die length          = 
| word size           = 64 bit
| core count          = 2
| thread count        = 4
| max cpus            = 1
| max memory          = 8 GiB
}}
'''Core i5-520UM''' is a {{arch|64}} [[x86]] [[dual-core]] mobile microprocessor introduced by [[Intel]] in [[2010]]. This processor, which is based on the {{intel|Westmere|l=arch}} microarchitecture ({{intel|Arrandale|l=core}} core), is manufactured on a [[32 nm process]]. This MPU operates at a base frequency of 1.07 GHz with a {{intel|Turbo Boost}} frequency of 1.87 GHz and a TDP of 18 W. This processor incorporated the {{intel|HD Graphics (Ironlake)}} [[IGP]] on the same package operating at a base frequency of 166.00 MHz and a burst frequency of 500.00 MHz.
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Core i5-520UM - Intel#package + and Core i5-520UM - Intel#io +
base frequency	1,066.66 MHz (1.067 GHz, 1,066,660 kHz) +
bus links	1 +
bus rate	2,500 MT/s (2.5 GT/s, 2,500,000 kT/s) +
bus type	DMI 1.0 +
chipset	Ibex Peak +
clock multiplier	8 +
core count	2 +
core family	6 +
core model	37 +
core name	Arrandale +
core stepping	C2 + and K0 +
cpuid	0x20655 +
designer	Intel +
device id	0x0046 +
die area	81 mm² (0.126 in², 0.81 cm², 81,000,000 µm²) +
family	Core i5 +
first announced	January 7, 2010 +
first launched	January 7, 2010 +
full page name	intel/core i5/i5-520um +
has ecc memory support	false +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Extended Page Tables +, Flex Memory Access +, Hyper-Threading Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Trusted Execution Technology + and Turbo Boost Technology 1.0 +
has intel enhanced speedstep technology	true +
has intel flex memory access support	true +
has intel trusted execution technology	true +
has intel turbo boost technology 1 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	HD Graphics (Ironlake) +
integrated gpu base frequency	166 MHz (0.166 GHz, 166,000 KHz) +
integrated gpu designer	Intel +
integrated gpu execution units	12 +
integrated gpu max frequency	500 MHz (0.5 GHz, 500,000 KHz) +
isa	x86-64 +
isa family	x86 +
l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	4-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	8-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description	12-way set associative +
l3$ size	3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
ldate	January 7, 2010 +
manufacturer	Intel +
market segment	Mobile +
max cpu count	1 +
max junction temperature	378.15 K (105 °C, 221 °F, 680.67 °R) +
max memory	8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	2 +
max pcie lanes	16 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Westmere +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	i5-520UM +
name	Intel Core i5-520UM +
package	BGA-1288 +
part number	CN80617005352AA +
platform	Calpella +
process	32 nm (0.032 μm, 3.2e-5 mm) +
release price	$ 241.00 (€ 216.90, £ 195.21, ¥ 24,902.53) +
s-spec	SLBQP + and SLBSQ +
series	i5-500 +
smp max ways	1 +
supported memory type	DDR3-800 +
tdp	18 W (18,000 mW, 0.0241 hp, 0.018 kW) +
technology	CMOS +
thread count	4 +
transistor count	382,000,000 +
turbo frequency (1 core)	1,866.66 MHz (1.867 GHz, 1,866,660 kHz) +
turbo frequency (2 cores)	1,599.99 MHz (1.6 GHz, 1,599,990 kHz) +
word size	64 bit (8 octets, 16 nibbles) +