Editing intel/80486/486dx2-50

{{intel title|i486DX2-50}}
{{mpu
| name                = Intel i486DX2-50
| no image            = Yes
| image               = 
| image size          = 
| caption             = 
| designer            = Intel
| manufacturer        = Intel
| model number        = i486DX2-50
| part number         = A80486DX2-50
| part number 2       = MA80486DX2-50
| part number 3       = MQ80486DX2-50
| part number 4       = TQ80486DX250
| part number 5       = SB80486DX2-50
| market              = 
| first announced     = 
| first launched      = March 3, 1992
| last order          = 
| last shipment       = 

| family              = 80486
| series              = 486DX2
| locked              = 
| frequency           = 50 MHz
| bus type            = FSB
| bus speed           = 25 MHz
| bus rate            = 25 MT/s
| clock multiplier    = 2
| s-spec              = 
| s-spec es           = 
| s-spec qs           = 
| cpuid               = 

| microarch           = 80486
| platform            = 
| chipset             = 
| core name           = 486DX2
| core family         = 
| core model          = 
| core stepping       = 
| process             = 1 µm
| process 2           = 800 nm
| transistors         = 
| technology          = CMOS
| die size            = 
| word size           = 32 bit
| core count          = 1
| max cpus            = 1
| max memory          = 4 GB

| electrical          = Yes
| power               = 
| v core              = 5 V
| v core tolerance    = 
| temp max            = 85 °C
| temp min            = 0 °C

| packaging           = Yes
| package             = CPGA-168
| package type        = 
| package size        = CPGA
| package 2           = PQFP-196
| package type 2      = PQFP
| package 3           = SQFP-208
| package type 3      = SQFP
| socket              = Socket 1 
| socket 2            = Socket 2
| socket 3            = Socket 3
}}
'''i486DX2-50''' was a fourth-generation [[x86]] [[microprocessor]] introduced by [[Intel]] in 1992. This chip, which is based on the {{intel|microarchitectures/80486|80486 microarchitecture}}, had a clock doubler operating at 50 MHz, twice the bus frequency. Like the original i486DX, this chip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM).

== Cache ==
{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}}
{{cache info
|l1 cache=8 KB
|l1 break=1x8 KB
|l1 desc=4-way set associative
|l1 extra=(unified, write-through policy )
}}

== Graphics ==
This chip had no integrated graphics processing unit.

== Features ==
* {{intel|System Management Mode}} (SMM)

== See also ==
* {{intel|80486|80486 family}}
base frequency	50 MHz (0.05 GHz, 50,000 kHz) +
bus rate	25 MT/s (0.025 GT/s, 25,000 kT/s) +
bus speed	25 MHz (0.025 GHz, 25,000 kHz) +
bus type	FSB +
clock multiplier	2 +
core count	1 +
core name	486DX2 +
core voltage	5 V (50 dV, 500 cV, 5,000 mV) +
core voltage tolerance	5% +
cpuid	432 +, 433 +, 435 + and 436 +
designer	Intel +
family	80486 +
first launched	March 3, 1992 +
full page name	intel/80486/486dx2-50 +
instance of	microprocessor +
l1$ description	4-way set associative +
l1$ size	8 KiB (8,192 B, 0.00781 MiB) +
ldate	March 3, 1992 +
main image	+
main image caption	SB80486DX2-50 +
manufacturer	Intel +
max cpu count	1 +
max memory	4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max operating temperature	85 °C +
microarchitecture	80486 +
min operating temperature	0 °C +
model number	i486DX2-50 +
name	Intel i486DX2-50 +
part number	A80486DX2-50 +, MA80486DX2-50 +, MQ80486DX2-50 +, TQ80486DX250 + and SB80486DX2-50 +
power dissipation	3.88 W (3,880 mW, 0.0052 hp, 0.00388 kW) +
process	1,000 nm (1 μm, 0.001 mm) + and 800 nm (0.8 μm, 8.0e-4 mm) +
s-spec	SX626 +, SX627 +, SX641 +, SX721 +, SX738 +, SX749 +, SX760 +, SX761 +, SX768 +, SX808 +, SX825 +, SX912 +, SX920 + and SX954 +
s-spec (qs)	Q0382 + and Q0424 +
series	486DX2 +
smp max ways	1 +
technology	CMOS +
word size	32 bit (4 octets, 8 nibbles) +