Editing amd/microarchitectures/zen 4

{{amd title|Zen 4|arch}}
{{microarchitecture
|atype=CPU
|name=Zen 4
|designer=AMD
|manufacturer=TSMC
|process=5nm, 6nm
|predecessor=Zen 3
|predecessor link=amd/microarchitectures/zen 3
|successor=Zen 5
|successor link=amd/microarchitectures/zen 5
|succession=Yes
}}
'''Zen 4''' is a [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|Zen 3}}. See press release for details: [https://www.amd.com/en/press-releases/2022-08-29-amd-launches-ryzen-7000-series-desktop-processors-zen-4-architecture-the AMD Launches Ryzen 7000 Series Desktop Processors]

== History ==
[[File:next-horizon-zen3-4-roadmap.png|right|thumb|400px|Zen 4 on the roadmap.]]
Zen 4 was first mentioned by Forrest Norrod during AMD's EPYC One Year Anniversary webinar. During the next horizon event which was held on November 6, 2018, AMD stated that Zen 4 was at the design completion phase.

== Codenames ==
'''Product Codenames:'''
{| class="wikitable"
|-
! Core !! C/T !! Target
|-
| {{amd|Bergamo|l=core}} || Up to 128/256 || High-performance CSP server [[multiprocessors]]
|-
| {{amd|Genoa|l=core}} || Up to 96/192 || High-end server [[multiprocessors]]
|-
| {{amd|Storm Peak|l=core}} || Up to 64/128 || Workstation & enthusiasts market processors
|-
| {{amd|Raphael|l=core}} || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors
|-
| {{amd|Dragon Range|l=core}} || Up to 16/32 || High-end mobile processors with GPU
|-
| {{amd|Phoenix Point|l=core}} || Up to 8/16 || Mainstream desktop & mobile processors with GPU
|}

'''Architectural Codenames:'''
{| class="wikitable"
|-
! Arch !! Codename
|-
| Core || Persephone
|-
| CCD || Durango
|}

== Products ==
{{future information}}

{| class="wikitable"
|-
! Processor Series !! Cores/Threads !! Market
|-
| EPYC 9004 "{{amd|Genoa|l=core}}" || Up to 96/192 || High-end server [[multiprocessors]]
|-
| Ryzen Threadripper 7000 "{{amd|Storm Peak|l=core}}" || Up to 96/192 || Workstation & enthusiasts market processors
|-
| Ryzen 7000 "{{amd|Raphael|l=core}}" || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors
|-
| Ryzen 7000 APU "{{amd|Dragon Range|l=core}}" || Up to 16/32 || High-end mobile processors with GPU 
|-
| Ryzen 7000 APU "{{amd|Phoenix Point|l=core}}" || Up to 8/16 || Mainstream desktop & mobile processors with GPU 
|}

Cores using variant Zen 4 uarch:

{| class="wikitable"
|-
! Processor Series !! Cores/Threads !! Market
|-
| EPYC 9004 {{amd|Bergamo|l=core}} || Up to 128/256  || Cloud [[multiprocessors]] (smaller, almost half-size Zen 4c [referred to as “Zen 4D” in leaks] core sacrificing half of the L3 cache.)
|}

== Process Technology ==
Zen 4 is fabricated using both the [[5nm]] node for the Core Compute Die (CCD) and the [[6nm]] node for the Input/Output Die (IOD) by [[TSMC]].

== Architecture ==
{{future information}}

=== Key changes from {{\\|Zen 3}} ===
* Core
** AVX-512 instructions support (256-bit datapaths<ref name="ryzen-7000-preview"/>)
** L1 and L2 DTLB size increased from 64 to 72 and 2,048 to 3,072 entries
** L2 cache doubled from 512 KiB to 1 MiB per core
** Max. physical and linear address size raised from 48 to 52 and 57 bits respectively
** Improved cache load, write and prefetch from/to register (less latency)
** Higher Transistor Density, due to 5nm process
** Capable of higher all-core clockspeeds (shown by AMD to reach 5GHz+ on all cores)
** Larger integer register file (from 192 to 224), floating-point register file (from 160 to 192) and reorder buffer (from 256 to 320 entries)
* Package
** Raised maximum core/thread count from 64/128 to at least 96/192 (EPYC 9004) (Bergamo supports 128 cores but preliminary data shows a slightly altered architecture featuring cores that take up less space)
** Support for DDR5 memory and PCIe Gen 5
** New sockets {{amd|AM5|l=pack}} (client), {{amd|SP5|l=pack}} (server), {{amd|SP6|l=pack}} (server), {{amd|FP7|FP7/FP7r2|l=pack}} (mobile)
** RDNA2-based iGPU with 2 compute units (128 stream processors)

=== New Instructions ===
Zen 4 introduced the following ISA enhancements:

<!--Update AVX-512 article when confirmed.-->
* {{x86|AVX-512}} - 512-bit Vector Instructions
** {{x86|AVX512F}} - Foundation (first introduced with [[Intel]] {{intel|skylake (server)|Skylake|l=arch}})
** {{x86|AVX512CD}} - Conflict Detection Instructions ({{intel|Skylake X|l=core}})
** {{x86|AVX512VL}} - Vector Length Extensions (Skylake X)
** {{x86|AVX512DQ}} - Doubleword and Quadword Instructions (Skylake X)
** {{x86|AVX512BW}} - Byte and Word Instructions (Skylake X)
** {{x86|AVX512 IFMA}} - Integer Fused Multiply-Add ({{intel|Cannon Lake|l=arch}})
** {{x86|AVX512 VBMI}} - Vector Bit Manipulation Instructions (Cannon Lake)
** {{x86|AVX512 VPOPCNTDQ}} - Vector Population Count Instruction ({{intel|ice lake (server)|Ice Lake|l=arch}})
** {{x86|AVX512 BITALG}} - Bit Algorithms (Ice Lake)
** {{x86|AVX512 VBMI2}} - Vector Bit Manipulation Instructions 2 (Ice Lake)
** {{x86|AVX512 VNNI}} - Vector Neural Network Instructions (Ice Lake)
** {{x86|AVX512 BF16}} - [[bfloat16|BFloat16]] Instructions ({{intel|Cooper Lake|l=arch}})
** ''Not supported'': AVX512ER, AVX512PF ({{intel|Knights Landing|l=arch}}); AVX512 4VNNIW, 4FMAPS ({{intel|Knights Mill|l=arch}}); VP2INTERSECT ({{intel|Tiger Lake|l=arch}})
* GFNI - Galois Field New Instructions (first introduced with [[Intel]] {{intel|ice lake (server)|Ice Lake|l=arch}})
** <code>VGF2P8AFFINEQB</code> - Galois field affine transformation
** <code>VGF2P8AFFINEINVQB</code> - Galois field affine transformation inverse
** <code>VGF2P8MULB</code> - Galois field multiply bytes

=== Memory Hierarchy ===
==== Data and Instruction Caches ====
* L0 Op Cache:
** 6.75K<ref name="ryzen-7000-preview"/> Ops per core, 8-way(?) set associative
** 9 Op line size(?)
** Parity protected
* L1I Cache:
** 32 KiB per core, 8-way set associative
** 64 B line size
** Parity protected
* L1D Cache:
** 32 KiB per core, 8-way set associative
** 64 B line size
** Write-back policy
** ? cycles latency for Int
** ? cycles latency for FP
** ECC
* L2 Cache:
** 1 MiB per core, 8-way set associative
** 64 B line size
** Write-back policy
** Inclusive of L1(?)
** 14 cycles latency
** {{abbr|DEC-TED}} ECC, tag & state arrays {{abbr|SEC-DED}}<!--7 check bits for 42 tag bits; AMD-55901-0.97 Sec 3.5-->
* L3 Cache:
<!--** "{{amd|Genoa|l=core}}": ? MiB/CCX, up to ? MiB total-->
** Shared by all cores in the CCX, configurable
** 16-way set associative
** 64 B line size
** L2 [[victim cache]](?)
** Write-back policy
** 50 cycles average load-to-use latency
** DEC-TED ECC, tag array & shadow tags SEC-DED<!--AMD-55901-0.97 Sec 3.5-->
** QoS Monitoring and Enforcement

==== Translation Lookaside Buffers ====
* ITLB
** 64 entry L1 TLB, fully associative, all page sizes
** 512 entry L2 TLB, ?-way set associative
*** 4-Kbyte, 2-Mbyte, and 4-Mbyte pages
** Parity protected
* DTLB
** 72 entry L1 TLB, fully associative, all page sizes
** 3,072 entry L2 TLB, 12-way set associative
*** 4-Kbyte, 2-Mbyte, and 4-Mbyte pages, PDEs to speed up table walks(?)
** Parity protected

4-Mbyte pages require two 2-Mbyte entries in all TLBs. <!--TBD: All caches and TLBs are competitively shared in multi-threaded mode.-->

==== System DRAM ====
* Ryzen 7000 "{{amd|Raphael|l=core}}":
** Up to PC5-41600 (DDR5-5200) without overclocking
* EPYC 9004 "{{amd|Genoa|l=core}}":
** 12 channels per socket, two 40-bit DDR5 subchannels per channel
** Up to 24 DIMMs, max. ?&nbsp;TiB
** Up to PC5-44800 (DDR5-5600)
** {{abbr|SR}}/{{abbr|DR}} {{abbr|RDIMM}}, {{abbr|4R}}/{{abbr|8R}} {{abbr|LRDIMM}}, {{abbr|3DS DIMM}}
** ECC supported (x4, x8, x16, chipkill)<!--AMD-55901-0.97 Sec 3.7-->
** DRAM bus parity and write data CRC options<!--ibid-->

Sources: <ref name="amd-55901-ppr-1910"/>

== All Zen 4 Processors ==
<!-- NOTE:
This table is generated automatically from the data in the actual articles.
If a microprocessor is missing from the list, an appropriate article for it needs to be
created and tagged accordingly.
Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable">
{{comp table header|main|14:List of all Zen 4-based Processors}}
{{comp table header|cols|Family|Codename|{{abbr|C|Cores}}|{{abbr|T|Threads}}|L2|L3|Base|Turbo|Memory|{{abbr|TDP}}|Launched|Price|{{abbr|OPN}}}}
{{comp table header|lsep|14:[[Uniprocessors]]}}
{{#ask: [[Category:microprocessor models by amd]] [[microarchitecture::Zen 4]] [[max cpu count::1]]
|?full page name
|?model number
|?microprocessor family
|?core name
|?core count
|?thread count
|?l2$ size
|?l3$ size
|?base frequency#GHz
|?turbo frequency#GHz
|?supported memory type
|?tdp
|?first launched
|?release price
|?part number
|sort=model number
|format=template
|template=proc table 3
|userparam=15
|mainlabel=-
|valuesep=,<br/>
}}
{{comp table header|lsep|14:[[Multiprocessors]] (dual-socket)}}
{{#ask: [[Category:microprocessor models by amd]] [[microarchitecture::Zen 4]] [[max cpu count::>>1]]
|?full page name
|?model number
|?microprocessor family
|?core name
|?core count
|?thread count
|?l2$ size
|?l3$ size
|?base frequency#GHz
|?turbo frequency#GHz
|?supported memory type
|?tdp
|?first launched
|?release price
|?part number
|sort=model number
|format=template
|template=proc table 3
|userparam=15
|mainlabel=-
|valuesep=,<br/>
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[microarchitecture::Zen 4]]}}
</table>
{{comp table end}}

== Designers ==
* Mike Clark(?), chief architect

== Bibliography ==

== References ==
<references>
<ref name="amd-55901-ppr-1910">{{cite techdoc|title=Processor Programming Reference (PPR) for AMD Family 19h Models 10h, Revision A0 Processors|publ=AMD|pid=55901|rev=0.97|date=2021-05-30}}</ref>
<ref name="ryzen-7000-preview">{{cite techdoc|title=Ryzen 7000 Desktop Preview|url=https://www.angstronomics.com/p/ryzen-7000-desktop-preview|publ=Angstronomics|date=2022-08-29}}</ref>
</references>

== See Also ==
* AMD {{\\|Zen}}, {{\\|Zen 2}}, {{\\|Zen 3}}
* Intel {{intel|Meteor Lake|l=arch}}
codename	Zen 4 +
designer	AMD +
full page name	amd/microarchitectures/zen 4 +
instance of	microarchitecture +
manufacturer	TSMC +
microarchitecture type	CPU +
name	Zen 4 +
process	5 nm (0.005 μm, 5.0e-6 mm) + and 6 nm (0.006 μm, 6.0e-6 mm) +