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Mongoose 3 (M3) - Microarchitectures - Samsung
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Mongoose 3 µarch
General Info
Arch TypeCPU
DesignerSamsung
ManufacturerSamsung
Introduction2018
Process10 nm
Core Configs4
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Decode6-way
Instructions
ISAARMv8
Succession

Mongoose 3 (M3) is the successor to the Mongoose 2, a 10 nm ARM microarchitecture designed by Samsung for their consumer electronics.

Process Technology[edit]

The M3 was fabricated on Samsung's second generation 10LPP (Low Power Plus) process.

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
GCC -march=armv8-a+crypto -mtune=exynos-m3

Architecture[edit]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Mongoose 1/M2[edit]

  • 10nm 10LPP process (from 1st gen 10LPP)
  • Core
    • Front-end
      • larger instruction queue (40 entries, up from 24)
      • 6-way decode (from 4)
      • µOP fusion
        • new fuse address generation and memory µOP support
        • new fuse literal generation µOP support
    • Back-end
      • Larger ReOrder buffer (228 entries, from 96 entries)
      • New fastpath logical shift of up to 3 places
      • Larger dispatch window (12 µOP/cycle, from 9)
      • Larger Integer physical register file
      • Larger FP physical register
      • Integer cluster
        • 9 pipes (from 7)
          • New pipe for a second load unit added
          • New pipe for a second ALU with 3-operand support and MUL/DIV
          • Double throughput for most integer operations
      • Floating Point cluster
        • 3 pipes (From 3)
          • Throughput of most FP operation have increased by 50% or doubled
          • Additional EUs
            • crypto EU, simple vector EU, vector shuffle/shift/mul, new FP store, new FP conversion
    • Memory subsystem
      • New L3 Cache
        • 4 MiB
      • 2x bandwidth (32B (2x16B)/cycle from 16B/cycle)
        • fast paired 128-bit loads and stores
  • branch misprediction penalty increased (16 cycles, from 14)

This list is incomplete; you can help by expanding it.

Block Diagram[edit]

Individual Core[edit]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

mongoose 3 block diagram.svg

Memory Hierarchy[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Core[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

All M3 Processors[edit]

 List of M3-based Processors
 Main processorIntegrated Graphics
ModelFamilyLaunchedArchCoresFrequencyTurboGPUFrequency
9810Exynos25 February 2018Cortex-A55, Mongoose 382.9 GHz
2,900 MHz
2,900,000 kHz
, 1.9 GHz
1,900 MHz
1,900,000 kHz
Mali-G72600 MHz
0.6 GHz
600,000 KHz
Count: 1


References[edit]

  • LLVM: lib/Target/AArch64/AArch64SchedExynosM3.td
codenameMongoose 3 +
core count4 +
designerSamsung +
first launched2018 +
full page namesamsung/microarchitectures/mongoose 3 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerSamsung +
microarchitecture typeCPU +
nameMongoose 3 +
process10 nm (0.01 μm, 1.0e-5 mm) +