Semiconductor & Computer Engineering
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MC14500 ISA - Motorola
| MC14500 ISA | |
| Developer | Motorola |
| Implementation | MC14500 |
| Dev model | proprietary |
| Data word size | 1 bit 0.125 octets
0.25 nibbles |
| Instruction word size | 4 bit 0.5 octets
|
| Instructions | 16 |
| Introduction | 1976 |
| Version | 1 |
| Format | register-memory |
| Endianness | bi-endian |
| Registers | 1 |
| SPRs | 1 RR |
| ISAs • By Company • By Inst • By Data | |
The MC14500 ISA is an instruction set architecture used in the MC14500 family of microprocessor. This ISA consists of just 4-bit opcodes forming a total of 16 instructions.
Registers[edit]
The MC14500B has a single register: result register (RR) which always stores the value of the intermediate operation that has been performed. RR can be read directly from pin 15 at any time. RR is also always used as the 2nd operand to any binary ALU operation.
Instruction Set[edit]
| MC14500 ISA | ||
|---|---|---|
| Mnemonic | Opcode | Action |
| NOPO | 0x0 | RR → RR ; Flag 0 → 1 |
| LD | 0x1 | Data → RR |
| LDC | 0x2 | Data → RR |
| AND | 0x3 | RR · Data → RR |
| ANDC | 0x4 | RR · Data → RR |
| OR | 0x5 | RR + Data → RR |
| ORC | 0x6 | RR + Data → RR |
| XNOR | 0x7 | If RR = Data, RR → 1 |
| STO | 0x8 | RR → Data ; Write → 1 |
| STOC | 0x9 | RR → Data ; Write → 1 |
| IEN | 0xA | Data → IEN |
| OEN | 0xB | Data → OEN |
| JMP | 0xC | Flag JMP → 1 |
| RTN | 0xD | Flag RTN → 1 |
| SKZ | 0xE | If RR = 0, Skip next instruction |
| NOPF | 0xF | RR → RR ; Flag F → 1 |
See also[edit]
Facts about "MC14500 ISA - Motorola"
| designer | Motorola + |
| first launched | 1976 + |
| full page name | motorola/mc14500/isa + |
| implementation | MC14500 + |
| instance of | instruction set architecture + |
| instruction count | 16 + |
| instruction word size | 4 bit (0.5 octets) + |
| name | MC14500 + |
| word size | 1 bit (0.125 octets, 0.25 nibbles) + |