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Amber Lake - Microarchitectures - Intel
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Amber Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionJune, 2018
Process14 nm
Core Configs2
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache256 KiB/core
4-way set associative
L3 Cache2 MiB/core
Up to 16-way set associative
Cores
Core NamesWhiskey Lake U
Succession
Contemporary
Coffee Lake
Whiskey Lake
Cannon Lake

Amber Lake is a microarchitecture designed by Intel as a successor to Kaby Lake for extremely-low power mobile devices, launched concurrently with Coffee Lake and Whiskey Lake.

Codenames[edit]

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Core Abbrev Description Graphics Target
Amber Lake Y AML-Y Extremely-low power GT2 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room

Brands[edit]

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Release Dates[edit]

Amber Lake was introduced at Computex 2018 on June 5.

Technology[edit]

Amber Lake is fabricated on 3rd generation improved 14++ process.

Compatibility[edit]

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Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
ICC -march=skylake -mtune=skylake
GCC -march=skylake -mtune=skylake
LLVM -march=skylake -mtune=skylake
Visual Studio /arch:AVX2 /tune:skylake

CPUID[edit]

Core Extended
Family
Family Extended
Model
Model
Y 0 0x6  ?  ?
Family 6 Model ?

Architecture[edit]

Key changes from Kaby Lake[edit]

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Overview[edit]

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