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Godson-2G
Godson-2G chip
General Info
Designer	Loongson
Manufacturer	STMicroelectronics
Model Number	2G
Market	Desktop
Introduction	April, 2009 (announced) November, 2010 (launched)
General Specs
Family	Godson 2
Series	Godson 2
Frequency	1,000 MHz
Bus type	HyperTransport 1.0
Bus speed	400 MHz
Clock multiplier	2.5
Microarchitecture
ISA	MIPS64 (MIPS)
Microarchitecture	GS464
Core Name	GS464
Process	65 nm
Transistors	100,000,000
Technology	CMOS
Die	53.54 mm²
Word Size	64 bit
Cores	1
Threads	1
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Power dissipation	3 W

Godson-2G (龙芯2G) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in late-2010, the Godson-2G operates at up to 1 GHz consuming up to 3 W. This chip was manufactured on STMicroelectronics' 65 nm process.

This specific models incorporates a considerably larger 2nd level cache compared to the rest of the Godson 2 family along with an extended number of additional interfaces in a relatively large package. The Godson-2G integrates the majority of the southbridge on-die.

Cache

Main article: GS464 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 4-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 4-way set associative   L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     1x1 MiB 4-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-800 Supports ECC Yes Max Mem 4 GiB Controllers 1 Channels 1 Max Bandwidth 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s Bandwidth Single 11.92 GiB/s

Expansions

This chip has integrated HyperTransport 1.0 operating at 400 MHz.

[Edit/Modify Expansions Info]

	Expansion Options
	PCI Width 32 bit Clock 66 MHz PCI-X Width 32 bit Clock 133 MHz LPC Revision 1.1

Die Shot

• 65 nm process
• 100,000,000 transistors
• 53.54 mm² die size

References

• Zhao, Ji-Ye, et al. "Physical Design Methodology for Godson-2G Microprocessor." Journal of Computer Science and Technology 25.2 (2010): 225-231.
• Weiwu Hu, Yunji Chen. "GS464V: A High-Performance Low-Power XPU with 512-Bit Vector Extension". HotChips 22 (2010).
• Loongson Technology, "龙芯芯片产品技术白皮书" ("Godson chip product technology white paper")