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Intel Core i7-660LM
General Info
Designer	Intel
Manufacturer	Intel
Model Number	i7-660LM
Part Number	CN80617004857AA
S-Spec	SLBSW
Market	Mobile
Introduction	September 13, 2010 (announced) September 13, 2010 (launched)
End-of-life	April 05, 2012 (last order) October 08, 2012 (last shipment)
Release Price	$346.00
Shop	Amazon
General Specs
Family	Core i7
Series	i7-600
Locked	Yes
Frequency	2,266.66 MHz
Turbo Frequency	Yes
Turbo Frequency	3,066.66 MHz (1 core), 2,799.99 MHz (2 cores)
Bus type	DMI 1.0
Bus rate	1 × 2.5 GT/s
Clock multiplier	17
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Westmere
Platform	Calpella
Chipset	Ibex Peak
Core Name	Arrandale
Core Family	6
Core Model	37
Core Stepping	K0
Process	32 nm
Transistors	382,000,000
Technology	CMOS
Die	81 mm²
Word Size	64 bit
Cores	2
Threads	4
Max Memory	8 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	25 W
Tjunction	0 °C – 105 °C
Packaging
Package BGA-1288 (BGA) Dimension 34 mm x 28 mm x 2.1 mm Pitch 0.7 mm Pin Count 1288

Core i7-660LM is a 64-bit dual-core x86-64 mobile microprocessor designed by Intel and introduced in early 2010. This chip is a first-generation Core i7 processor based on the Westmere microarchitecture and is manufactured on a 32 nm process. This processor operated at a based frequency of 2.26 GHz with a turbo frequency of 3.06 GHz and a TDP of 25 W. This MPU came with a HD Graphics (Ironlake) IGP operating at 266 MHz with a max burst frequency of 566 MHz.

Cache

Main article: Westmere § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 4-way set associative write-back L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative write-back L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 8-way set associative write-back L3$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     2x2 MiB 16-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1066 Supports ECC No Max Mem 8 GiB Controllers 1 Channels 2 Max Bandwidth 15.88 GiB/s 16,261.12 MiB/s 17.051 GB/s 17,051.02 MB/s 0.0155 TiB/s 0.0171 TB/s Bandwidth Single 7.942 GiB/s Double 15.88 GiB/s Physical Address (PAE) 36 bit

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
	PCIe Revision 2.0 Max Lanes 16 Configs 1x16

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU HD Graphics (Ironlake) Designer Intel Device ID 0x0046 Execution Units 12 Max Displays 2 Frequency 266 MHz 0.266 GHz 266,000 KHz Burst Frequency 566 MHz 0.566 GHz 566,000 KHz Standards DirectX 10.1 OpenGL 2.1 Additional Features Intel Flexible Display Interface (FDI) Intel Clear Video Intel Clear Video HD

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AES AES Encryption Instructions x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 1.0 Turbo Boost Technology 1.0 EIST Enhanced SpeedStep Technology TXT Trusted Execution Technology (SMX) vPro Intel vPro VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) Flex Memory Flex Memory Access FMA Fast Memory Access (w\ GMCH)