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Oracle's out the chip design business
Over a week ago we've tweeted the news that Oracle will be leaving the chip design business, at least for SPARC. Our source is someone in the know that we trust. Unfortunately Oracle has done this very quietly and without making any formal press statements.
This changed this week when on September 5th Oracle published an updated roadmap. The roadmap can be viewed here: http://www.oracle.com/us/products/servers-storage/servers/sparc/oracle-sparc/sparc-roadmap-slide-2076743.pdf
Take a note to the major change:
- Oracle M8 is finally announced https://www.oracle.com/corporate/pressrelease/oracle-sparc-m8-091817.html --David (talk) 10:04, 19 September 2017 (EDT)
Apple A11 Bionic
Apple just announced their "A11 Bionic" processor which will be used in an iPhone 8 and 8 Plus. 6 cores (2 big, 4 little), 64-bit, 4.3B xtors. The event can be watched here: https://www.apple.com/apple-events/september-2017/. --Inject (talk) 18:45, 12 September 2017 (EDT)
- The two extra little cores is just for marketing. "Hey we have 70% more multi-thread performance". I guess all the Android octa/deca-core marketing bullshit managed to get the best of them. --At32Hz (talk) 21:57, 12 September 2017 (EDT)
- Lots of marketing talk throughout the keynote. "600 GOPS" for the NPU how do we even compare that to anything? What does a "3 core GPU design" even mean? what do "cores" mean in this context anyway? those area clearly not shaders or alike. It's all so ambiguous. Then we have the actual Monsoon and Mistral architectures that we know nothing about. I guess we'll need to get an actual iphone and run our own code to reverse engineer everything. --David (talk) 22:16, 12 September 2017 (EDT)
NDA broken/lifted, Coffee Lake announced early
Since someone can't follow an embargo and leaked the slide deck early, Intel decided to announce Coffee Lake early. For the most part, we've had all the info already since the leaks happened to be spot-on so we've already had that info listed anyway. If you have anything to add, feel free to head to the Coffee Lake article. --David (talk) 12:23, 26 September 2017 (EDT)
U54-MC Coreplex IP
SiFive Launches First RISC-V Based CPU Core with Linux Support
"Inventors of RISC-V Unveil U54-MC Coreplex IP, a 64-Bit Multicore CPU Designed for Embedded Applications that Require a Full Operating System"