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- |isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AES}} !! [[IGP]] !! {{intel|Turbo Boost|TBT}} !! [[ECC]]84 KB (13,075 words) - 00:54, 29 December 2020
- |isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]79 KB (11,922 words) - 06:46, 11 November 2022
- |isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]30 KB (4,192 words) - 13:48, 10 December 2023
- |isa=x86-64 ! Cores !! Unlocked !! {{x86|AVX2}} !! [[SMT]] !! [[IGP]] !! [[ECC]] !! [[Multiprocessing|MP]]57 KB (8,701 words) - 22:11, 9 October 2022
- {{x86 title|Extensions}}{{x86 isa main}} The [[x86]] [[instruction set architecture|ISA]] has gone through numerous iterations6 KB (764 words) - 08:53, 7 June 2020
- {{x86 title|Advanced Vector Extensions 512 (AVX-512)}}{{x86 isa main}} ...ber of {{arch|512}} [[SIMD]] [[x86]] [[instruction set]] extensions. The {{x86|extensions}} were formally introduced by [[Intel]] in July [[2013]] with fi83 KB (13,667 words) - 15:45, 16 March 2023
- |isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{x86|AVX-512}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]52 KB (7,651 words) - 00:59, 6 July 2022
- |isa=x86-64 ...'''), the successor to {{\\|Palm Cove}}, is a high-performance [[10 nm]] [[x86]]-64 core microarchitecture designed by [[Intel]] for an array of server an34 KB (5,187 words) - 06:27, 17 February 2023