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  • amd/microarchitectures/vega
    *Tile based rendering
    4 KB (510 words) - 12:42, 16 June 2020
  • intel/microarchitectures/skylake (server)
    ...ough each of the rows and columns allowing for a shortest path between any tile, reducing latency, and improving the bandwidth. Those processors are offere :[[File:skylake sp mesh core tile zoom with client shown.png|1000px]]
    52 KB (7,651 words) - 00:59, 6 July 2022
  • nvidia/tegra/xavier
    The chip has an [[ISP]] with native full-range [[HDR]] support and [[tile rendering]] capable of processing at 1.5 GPIX/s.
    8 KB (1,263 words) - 03:08, 9 December 2019
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