• intel/microarchitectures/bonnell
  |cache=Yes should probably added at one point:
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/silvermont
  | cache = Yes * {{x86|MOVBE|<code>MOVBE</code>}} - Move Big-Endian instruction
  9 KB (1,160 words) - 09:35, 25 September 2019
• intel/microarchitectures/broadwell (client)
  |cache=Yes ...part identical to {{\\|Haswell}} with several enhancements, including new instruction set extensions.
  14 KB (1,891 words) - 14:37, 6 January 2022
• intel/microarchitectures/haswell (client)
  |cache=Yes * Cache
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  | {{intel|Sandy Bridge E|l=core}} || SNB-E || Workstations & entry-level servers ...="2" | {{intel|Celeron}} || style="text-align: left;" rowspan="2" | Entry-level Budget || [[1 cores|1]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  |side cache=128 MiB |side cache per=package
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  |side cache=64 MiB |side cache per=package
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/coffee lake
  ...=core}} || CFL-E || Mehlow || Workstation || GT2 || Workstations and entry-level servers ...(2015).png|50px|link=intel/celeron]] || {{intel|Celeron}} || 4xxx || Entry-level Budget || [[dual-core|Dual]] || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} |
  30 KB (4,192 words) - 13:48, 10 December 2023
• amd/microarchitectures/k6
  ** 2-level predictor with 8192 entry branch history table *** Does not store target addresses. Target addresses are calculated during instruction decode
  4 KB (578 words) - 18:57, 22 May 2019
• amd/microarchitectures/zen
  | [[File:amd ryzen 3 logo.png|75px|link=Ryzen 3]] || {{amd|Ryzen 3}} || Entry level Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk | desc 5 = '''Performance Level'''<br><table><tr><td style="width: 50px;">'''9'''</td><td>Extreme (Ryzen Th
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  | [[File:amd ryzen 3 logo.png|75px|link=Ryzen 3]] || {{amd|Ryzen 3}} || Entry level Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tch Zen 2 inherits most of the design from {{\\|Zen+}} but improves the instruction stream bandwidth and floating-point throughput performance.
  57 KB (8,701 words) - 22:11, 9 October 2022
• intel/microarchitectures/gen9.5
  ...vels of performance. Some models also support an additional [[eDRAM]] side cache. ...ontains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  ...vels of performance. Some models also support an additional [[eDRAM]] side cache. ...ontains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.
  33 KB (4,255 words) - 17:41, 1 November 2018
• ibm/microarchitectures/power9
  ** Instruction grouping at dispatch has been removed * Cache
  14 KB (1,905 words) - 23:38, 22 May 2020
• phytium/microarchitectures/xiaomi
  |cache=Yes * Large scale cache coherency
  7 KB (940 words) - 00:12, 8 March 2021
• dec/microarchitectures/alpha 21064
  ...ementation]]. In particular, the "Alpha" refers to [[DEC]]'s [[Alpha AXP]] instruction set architecture while the "21064" refers to a "21st century"-ready {{arch| ...r CMOS-3 process ([[1 µm]]). For that reason those chips also had reduced cache amount, in addition to no FPU support.
  4 KB (527 words) - 02:09, 4 August 2017
• intel/microarchitectures/skylake (server)
  ...).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || [[6 cores|6]] - [[8 cores|8]] || {{tchk ...LFLUSHOPT</code>}} - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..)
  52 KB (7,651 words) - 00:59, 6 July 2022
• amd/microarchitectures/zen+
  * Cache ** Improved cache prefetch
  11 KB (1,613 words) - 08:39, 3 March 2024
• pezy/pezy-scx
  ...The PEs do not maintain [[cache-coherency]] and there is no per-PE [[data cache]]. Complex instructions are processed by the Special Function Units (SFU) l ...2 KiB of [[level 1 data cache]]. Each '''City''' is made of 64 KiB of [[L2 cache]], a number of special function units, and 4 smaller blocks called "Village
  6 KB (838 words) - 09:33, 9 May 2019
• intel/microarchitectures/cascade lake
  ...).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || 6 || {{tchk|no}} || {{tchk|no}} || {{tc ** New {{x86|CPUID}} Level Type field for "die"
  32 KB (4,535 words) - 05:44, 9 October 2022

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