• intel/microarchitectures/sandy bridge (client)
  *** Instruction Queue Sandy Bridge [[TLB]] consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  **** instruction window is now 64 Bytes (from 32) Skylake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  Kaby Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a | Stream Processors || 1,536 || 1,280
  38 KB (5,431 words) - 10:41, 8 April 2024
• amd/microarchitectures/zen
  ** Larger instruction scheduler * <code>{{x86|ADX}}</code> - Multi-Precision Add-Carry Instruction extension
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  ...inherits most of the design from {{\\|Zen+}} but improves the instruction stream bandwidth and floating-point throughput performance. *** 0.5x L1 instruction cache (32 KiB, down from 64 KiB)
  57 KB (8,701 words) - 22:11, 9 October 2022
• intel/microarchitectures/gen9.5
  ...can be passed directly through registers or by using the URB. The Command Stream also manages the allocation of the URB and supports the Constant URB Entry | Command Stream (CS) || The Command Stream stage is responsible for managing the 3D pipeline and passing commands down
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  ...can be passed directly through registers or by using the URB. The Command Stream also manages the allocation of the URB and supports the Constant URB Entry | Command Stream (CS) || The Command Stream stage is responsible for managing the 3D pipeline and passing commands down
  33 KB (4,255 words) - 17:41, 1 November 2018
• intel/microarchitectures/skylake (server)
  * {{x86|PCOMMIT|<code>PCOMMIT</code>}} - PCOMMIT instruction Skylake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a
  52 KB (7,651 words) - 00:59, 6 July 2022
• samsung/microarchitectures/m1
  ** 4-way instruction decode Mongoose 1 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a
  13 KB (1,962 words) - 14:48, 21 February 2019
• samsung/microarchitectures/m3
  *** Larger [[instruction queue]] (40 entries, up from 24) *** Larger [[instruction fetch]] (48B/cycle, up from 24B/cycle)
  20 KB (3,149 words) - 10:44, 15 February 2020
• cavium/microarchitectures/vulcan
  *** Dedicated instruction TLB ...our threads, a thread scheduler determines from which thread's instruction stream to operate on. This determination is done on each cycle with the help of th
  17 KB (2,449 words) - 22:11, 4 October 2019
• amd/microarchitectures/zen 4
  ...prefetchers for code and data, four integer/address and two floating point instruction schedulers, 3-way address generation, 5-way integer execution. 4-way 256-bi * {{abbr|APU}}s: RDNA2-based iGPU with 2 compute units (128 stream processors)
  13 KB (1,821 words) - 19:28, 13 November 2023
• arm holdings/microarchitectures/cortex-a76
  *** Decoupled from the instruction fetch *** Strictly inclusive of the L1 data cache & non-inclusive of the L1 instruction cache
  14 KB (2,183 words) - 17:15, 17 October 2020
• arm holdings/microarchitectures/cortex-a77
  ** 1.5x wider instruction fetch (6 instrs/cycle, up from 4) ** 1.5x wider instruction fetch (6 instrs/cycle, up from 4)
  17 KB (2,555 words) - 06:08, 16 June 2023
• arm holdings/microarchitectures/cortex-a78
  ** Additional instruction fusion cases **** New packaging scheme (improve instruction density)
  21 KB (3,067 words) - 09:25, 31 March 2022
• intel/configurable spatial accelerator
  ...or executes [[data flow graphs]] directly instead traditional sequential [[instruction streams]]. Unlike an [[FPGA]], the CSA supports full languages such as C++ ...an also be architectural interfaces such as instruction pointer, triggered instruction, or be a state machine based architectural interface. PEs can execute right
  14 KB (2,130 words) - 20:19, 2 October 2018
• nec/microarchitectures/sx-aurora
  ...feed the vector pipeline, the address generation unit can receive a vector instruction from the SPU in advance in order to calculate the address and disperse the ...stem tasks. Additionally, the SPU has to provide the VPU with a sufficient stream of operations in order to maintain a high sustained performance as well as
  16 KB (2,497 words) - 13:30, 15 May 2020
• intel/microarchitectures/sunny cove
  Sunny Cove TLB consists of a dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is ...hereby variable-length [[x86]] instructions are fetched from the [[level 1 instruction cache]], queued, and consequently get decoded into simpler, fixed-length [[
  34 KB (5,187 words) - 06:27, 17 February 2023
• tesla (car company)/fsd chip
  ...ously run on its own the entire neural network model until reaching a stop instruction which triggers an interrupt, letting the CPU post-process the results. ==== Instruction set ====
  13 KB (1,952 words) - 20:34, 16 September 2023
• centaur/microarchitectures/cha
  ** Instruction cache *** Instruction ROM
  24 KB (3,792 words) - 04:37, 30 September 2022

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