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Show new changes starting from 13:57, 30 November 2025
   
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30 November 2025

     08:50  intel/microarchitectures/skylake (server)‎ (diff | hist) . . (+732)‎ . . 95.24.55.169 (talk) (→‎Codenames)

28 November 2025

     15:01  intel/cpuid‎‎ (2 changes | history) . . (+1,338)‎ . . [95.24.48.143‎ (2×)]
      15:01 (cur | prev) . . (+447)‎ . . 95.24.48.143 (talk) (→‎Family 19)
      14:38 (cur | prev) . . (+891)‎ . . 95.24.48.143 (talk) (→‎Small Cores)

27 November 2025

     16:45  intel/cpuid‎‎ (3 changes | history) . . (+26)‎ . . [2a04:4e41:1801:3108::6cbb:7108‎; 95.24.48.143‎ (2×)]
      16:45 (cur | prev) . . (+13)‎ . . 95.24.48.143 (talk) (→‎Big Cores (Client))
      11:35 (cur | prev) . . (+2)‎ . . 95.24.48.143 (talk) (→‎Big Cores (Server))
      09:34 (cur | prev) . . (+11)‎ . . 2a04:4e41:1801:3108::6cbb:7108 (talk) (→‎Big Cores (Server): Add the codename Jaketown used by Intel for the Sandybridge server 0x06_2D, cf https://github.com/intel/perfmon/blob/main/mapfile.csv)
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