From WikiChip
Change Chip Infobox Values: microsoft/scorpio engine

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

General Chip[edit]

Future?If the chip has not been released yet, select "Yes", OTHERWISE LEAVE BLANK
TypeIf it's a microprocessor (default), LEAVE BLANK.
Top Info:
NameThe common name of the chip.
No ImageCheck this if we don't want to show an image placeholder
Main Image Upload file Main Image
Main Image SizeImage Size; normally leave blank!
Main Image 2 Upload file Main Image 2
Main Image 2 SizeImage 2 Size; normally leave blank!
Back Image Upload file Back Image
Back Image SizeImage Size; normally leave blank!
CaptionCaption for the image
General Info:
Designer





Designer(s) of the chip
Manufacturer





Manufacturer(s) of the chip
Model NumberModel number of the chip
Part Number

, ,
, ,
, ,
,
,

Part number(s) of the chip
S-Spec

, , ,
, , ,
, , ,
, ,

S-Spec numbers
S-Spec (QS)

, , ,
, , ,
, , ,
, ,

S-Spec Qualification Samples
Market



Market
Date AnnouncedThe date announced
Date LaunchedThe date launched
Last OrderLast date to order
Last ShipmentLast shippment
Release PricePrice of product on release (if not box/tray specific)
Release Price (tray)Price of product on release FOR A TRAY
Release Price (box)Price of product on release FOR A BOX
General Specs:
Family, Chip Family
SeriesChip Series
LockedIs it Locked?
Frequency

, ,
, ,
, ,
,

Base Frequency
(1 or more set frequencies, NOT turbo)
Turbo Frequency

1: , 2: , 3: ,
4: , 5: , 6: ,
7: , 8: , 9: ,
10: , 11: , 12: ,
13: , 14: , 15: ,
16: , 17: , 18: ,
19: , 20: , 21: ,
22: , 23: , 24: ,
25: , 26: , 27: ,
28: , 29: , 30: ,
31: , 32:

Turbo Frequency
(goes by active cores)
Turbo FrequencyTurbo Frequency
(NOT per core)
Bus typebus type
Bus speedbus speed
Bus rate × bus links × bus rate
Clock multiplierclock multiplier
CPUID

, , ,
,

CPUIDs
Microarchitecture:
ISA

ISA:
ISA Family:
ISA 2:
ISA 2 Family:

ISA
Microarchitecture

, ,
,

Microarchitecture
PlatformPlatform
Chipset

, ,
,

Chipset
Core Names

, ,
,

Core Names
Core family

, ,
,

Core family
Core model

, ,
,

Core model
Core stepping

, ,
,

Core stepping
Process

, ,
,

Process
TransistorsTransistors
TechnologyTechnology
Die

Area: (mm²)
Length: × Width:

Die
MCP


Die count:

Check this chip is in a multi-chip package
Word SizeWord Size
CoresCores
ThreadsThreads
Max MemoryMax Memory
Max Address MemMax Address Mem
Multiprocessing:
Max CPUsMax CPUs
SMP InterconnectSMP Interconnect
SMP Interconnect LinksSMP Interconnect Links
SMP Interconnect RateSMP Interconnect Rate
Electrical:
Power dissipationPower dissipation
Power dissipation (average)Power dissipation (average)
Power dissipation (idle)Power dissipation (idle)
Vcore

±
OR:
-

Core voltage
VI/O

± ,
, ,
,

I/O voltage
SDPSDP
TDP

, ,
,

TDP
Typical TDPTypical TDP
cTDP-Down

@

Configurable TDP-down & Frequency
cTDP-Up

@

Configurable TDP-up & Frequency
Temperature (°C)

Op Temp: -
Tjunction: -
Tcase: -
Tstorage: -
Tambient: -
TDTS: -

Temperatures (°C)
Packaging:
Package Module (DEPRECATED)



Package Module
e.g., {{packages/amd/socket am4}}
Package Info




Package Name, e.g. intel,fclga_3647.

A page name amd/packages/socket_am4 is also accepted.

List of package pages.
Succession
Predecessor

Pred:
Pred Link:
Pred2:
Pred2 Link:
Pred3:
Pred3 Link:
Pred4:
Pred4 Link:
Pred5:
Pred5 Link:

Predecessor Core
Successor

Succ:
Succ Link:
Succ2:
Succ2 Link:
Succ3:
Succ3 Link:
Succ4:
Succ4 Link:
Succ5:
Succ5 Link:

Successor Core
Contemporary

Cont:
Cont Link:
Cont2:
Cont2 Link:
Cont3:
Cont3 Link:
Cont4:
Cont4 Link:
Cont5:
Cont5 Link:

Contemporary Core

Neuromorphic Chip[edit]

Neuromorphic Chip Specs:
NeuronsNeuron Count
SynapsesSynapse Count
Cancel