Semiconductor & Computer Engineering
| Elbrus-4S | |
| |
| Developer | MCST |
| Type | Microprocessors |
| Introduction | 2014 (launch) |
| Architecture | Elbrus (VLIW), version 3 |
| Word size | 64 bit 8 octets
16 nibbles |
| Process | 65 nm 0.065 μm
6.5e-5 mm |
| Clock | 800 MHz |
| Package | HFCBGA 1600 |
| Socket | Surface mount |
| Succession | |
| ← | → |
| Elbrus-2S+ | Elbrus-8S |
Elbrus-4S (rus. Эльбрус-4С, code designation: 1891ВМ8Я) is an universal multi-core VLIW microprocessor with the Elbrus architecture, developed by the russian company MCST.
Overview[edit]
The «Elbrus-4S» processor contains 4 cores, level 2 cache memory with a total capacity of 8 megabytes, 3 memory controllers compliant with DDR3-1600, 3 interprocessor communication channels and an input-output channel. Each processor core executes 23 instructions per cycle. The processor contains hardware support for binary translation of 64-bit Intel/AMD codes. The peak processor performance is 25 Gflops for a 64-bit configuration and 50 Gflops for a 32-bit configuration[1]. The average power dissipation is 45 watts. The microprocessor is intended for use in personal computers and servers[2][3].
References[edit]
| designer | MCST + |
| first launched | 2014 + |
| full page name | MCST/elbrus-4s + |
| instance of | microprocessor family + |
| main designer | MCST + |
| name | Elbrus-4S + |
| package | HFCBGA 1600 + |
| process | 65 nm (0.065 μm, 6.5e-5 mm) + |
| socket | Surface mount + |
| word size | 64 bit (8 octets, 16 nibbles) + |