From WikiChip
Core i5-2560M - Intel
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| Core i5-2560M | |||||||||
| General Info | |||||||||
| Designer | Intel | ||||||||
| Manufacturer | Intel | ||||||||
| Model Number | i5-2560M | ||||||||
| Part Number | AV8062700839505 | ||||||||
| S-Spec | SR047 | ||||||||
| Market | Mobile | ||||||||
| Introduction | October, 2011 (announced) October, 2011 (launched) | ||||||||
| Shop | Amazon | ||||||||
| General Specs | |||||||||
| Family | Core i5 | ||||||||
| Series | i5-2000 | ||||||||
| Locked | Yes | ||||||||
| Frequency | 2,700 MHz | ||||||||
| Bus type | DMI 2.0 | ||||||||
| Bus rate | 4 × 5 GT/s | ||||||||
| Clock multiplier | 27 | ||||||||
| CPUID | 0x206A7 | ||||||||
| Microarchitecture | |||||||||
| ISA | x86-64 (x86) | ||||||||
| Microarchitecture | Sandy Bridge | ||||||||
| Platform | Sandy Bridge M | ||||||||
| Chipset | Cougar Point | ||||||||
| Core Name | Sandy Bridge M | ||||||||
| Core Family | 6 | ||||||||
| Core Model | 42 | ||||||||
| Core Stepping | J1 | ||||||||
| Process | 32 nm | ||||||||
| Transistors | 624,000,000 | ||||||||
| Technology | CMOS | ||||||||
| Die | 149 mm² | ||||||||
| Word Size | 64 bit | ||||||||
| Cores | 2 | ||||||||
| Threads | 4 | ||||||||
| Max Memory | 16 GiB | ||||||||
| Multiprocessing | |||||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||||
| Electrical | |||||||||
| Power (idle) | 3.1 W | ||||||||
| Vcore | 0.3 V-1.52 V | ||||||||
| TDP | 35 W | ||||||||
| Tjunction | 0 °C – 100 °C | ||||||||
| Tstorage | -25 °C – 125 °C | ||||||||
| Packaging | |||||||||
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Core i5-2560M is a dual-core mid-range performance mobile x86 microprocessor introduced by Intel in late 2011. This chip, which is fabricated on a 32 nm process based on the Sandy Bridge microarchitecture, operates at 2.7 GHz with a TDP of 35 Watts and a Turbo Boost frequency of up to ? GHz. The i5-2560M incorporates HD Graphics 3000 integrated graphics operating at 650 MHz with a burst frequency of 1.3 GHz and supports up to 16 GiB of dual-channel DDR3-1333 memory.
Cache[edit]
- Main article: Sandy Bridge § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
Expansion Options |
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Wireless[edit]
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Graphics[edit]
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Integrated Graphics Information
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| [Edit] Sandy Bridge (Gen6) Hardware Accelerated Video Capabilities | |||||||
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| Codec | Encode | Decode | |||||
| Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
| MPEG-2 (H.262) | ✘ | Main | Main, High | Up to 80 Mbps | |||
| MPEG-4 AVC (H.264) | Main | 4.1 | Up to 40 Mbps | Main, High | 4.1 | Up to 40 Mbps | |
| VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | Up to 40 Mbps | |||
Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Core i5-2560M - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-2560M - Intel#package + and Core i5-2560M - Intel#pcie + |
| base frequency | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
| bus links | 4 + |
| bus rate | 5,000 MT/s (5 GT/s, 5,000,000 kT/s) + |
| bus type | DMI 2.0 + |
| chipset | Cougar Point + |
| clock multiplier | 27 + |
| core count | 2 + |
| core family | 6 + |
| core model | 42 + |
| core name | Sandy Bridge M + |
| core stepping | J1 + |
| core voltage (max) | 1.52 V (15.2 dV, 152 cV, 1,520 mV) + |
| core voltage (min) | 0.3 V (3 dV, 30 cV, 300 mV) + |
| cpuid | 0x206A7 + |
| designer | Intel + |
| device id | 0x116 + |
| die area | 149 mm² (0.231 in², 1.49 cm², 149,000,000 µm²) + |
| family | Core i5 + |
| first announced | October 2011 + |
| first launched | October 2011 + |
| full page name | intel/core i5/i5-2560m + |
| has 4g support | true + |
| has advanced vector extensions | true + |
| has ecc memory support | false + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Flex Memory Access +, My WiFi Technology + and Identity Protection Technology + |
| has intel enhanced speedstep technology | true + |
| has intel flex memory access support | true + |
| has intel identity protection technology support | true + |
| has intel my wifi technology support | true + |
| has intel trusted execution technology | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has locked clock multiplier | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has wimax support | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| integrated gpu | HD Graphics 3000 + |
| integrated gpu base frequency | 650 MHz (0.65 GHz, 650,000 KHz) + |
| integrated gpu designer | Intel + |
| integrated gpu execution units | 12 + |
| integrated gpu max frequency | 1,300 MHz (1.3 GHz, 1,300,000 KHz) + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 12-way set associative + |
| l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
| ldate | October 2011 + |
| manufacturer | Intel + |
| market segment | Mobile + |
| max cpu count | 1 + |
| max junction temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
| max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) + |
| max memory bandwidth | 19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) + |
| max memory channels | 2 + |
| max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
| microarchitecture | Sandy Bridge + |
| min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
| model number | i5-2560M + |
| name | Core i5-2560M + |
| package | FCBGA-1023 + |
| part number | AV8062700839505 + |
| platform | Sandy Bridge M + |
| power dissipation (idle) | 3.1 W (3,100 mW, 0.00416 hp, 0.0031 kW) + |
| process | 32 nm (0.032 μm, 3.2e-5 mm) + |
| s-spec | SR047 + |
| series | i5-2000 + |
| smp max ways | 1 + |
| supported memory type | DDR3-1333 + and DDR3-1066 + |
| tdp | 35 W (35,000 mW, 0.0469 hp, 0.035 kW) + |
| technology | CMOS + |
| thread count | 4 + |
| transistor count | 624,000,000 + |
| word size | 64 bit (8 octets, 16 nibbles) + |