Edit Values |
Cavium CN3120-400 EXP |
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Designer | Cavium |
Manufacturer | TSMC |
Model Number | CN3120-400 EXP |
Part Number | CN3120-400BG868-EXP |
Market | Embedded |
Introduction | January 30, 2006 (announced) May 1, 2006 (launched) |
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Family | OCTEON |
Series | CN3100 |
Frequency | 400 MHz |
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ISA | MIPS64 (MIPS) |
Microarchitecture | cnMIPS |
Core Name | cnMIPS |
Process | 130 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 2 |
Threads | 2 |
Max Memory | 4 GiB |
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Max SMP | 1-Way (Uniprocessor) |
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Package | HSBGA-868 (BGA) |
Ball Count | 868 |
Interconnect | BGA-868 |
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The CN3120-400 EXP is a 64-bit dual-core MIPS communication microprocessor designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware accelerators for network processing such as compression & decompression, RegEx engine, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
- Main article: cnMIPS § Cache
[Edit/Modify Cache Info]
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Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
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L1$ | 80 KiB 81,920 B 0.0781 MiB
| L1I$ | 64 KiB 65,536 B 0.0625 MiB
| 2x32 KiB | 4-way set associative | |
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L1D$ | 16 KiB 16,384 B 0.0156 MiB
| 2x8 KiB | 64-way set associative | Write-through |
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| L2$ | 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB
| | | 1x256 KiB | 8-way set associative | |
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Memory controller[edit]
[Edit/Modify Memory Info]
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Integrated Memory Controller
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Max Type | DDR2-667 |
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Supports ECC | Yes |
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Max Mem | 4 GiB |
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Controllers | 1 |
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Channels | 1 |
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Width | 64 bit |
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Max Bandwidth | 4.97 GiB/s 5,089.28 MiB/s 5.336 GB/s 5,336.497 MB/s 0.00485 TiB/s 0.00534 TB/s
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Bandwidth |
Single 4.97 GiB/s
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Optional low-latency controller for content-based processing and meta data
[Edit/Modify Memory Info]
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Integrated Memory Controller
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Max Type | DDR2-667 |
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Supports ECC | Yes |
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Max Mem | 2 GiB |
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Controllers | 1 |
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Channels | 1 |
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Width | 16 bit |
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Max Bandwidth | 1.24 GiB/s 1,269.76 MiB/s 1.331 GB/s 1,331.44 MB/s 0.00121 TiB/s 0.00133 TB/s
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Bandwidth |
Single 1.24 GiB/s
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Expansions[edit]
Networking[edit]
Hardware Accelerators[edit]
Block diagram[edit]
Datasheet[edit]