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Difference between revisions of "zhongshan subor/fireflight"

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{{title|Z+ SoC - Zhongshan Subor}}
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{{title|FireFlight - Zhongshan Subor}}
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{{chip}}
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{{chip
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'''Z+ SoC''' is a semi-custom [[quad-core]] [[x86]] [[SoC]] designed by [[AMD]] for Zhongshan Subor for their gaming PC/consoles and introduced in mid-2018. The Z+ features four {{amd|Zen|l=arch}} cores operating at 3 GHz along with a 24-CU {{amd|vega|Radeon Vega|l=arch}} GPU operating at up to 1.3 GHz.
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|name=FireFlight
 +
|no image=Yes
 +
|designer=AMD
 +
|designer 2=Zhongshan Subor
 +
|model number=FireFlight
 +
|market=Console
 +
|market 2=Desktop
 +
|first announced=August 3, 2018
 +
|first launched=August 3, 2018
 +
|frequency=3,000 MHz
 +
|bus type=PCIe 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 +
|clock multiplier=30
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Zen
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=4
 +
|thread count=8
 +
|max cpus=1
 +
|max memory=8 GiB
 +
}}
 +
'''FireFlight''' is a semi-custom [[quad-core]] [[x86]] [[SoC]] designed by [[AMD]] for Zhongshan Subor for their gaming PC/consoles and introduced in mid-2018. The Z+ features four {{amd|Zen|l=arch}} cores operating at 3 GHz along with a 24-CU {{amd|vega|Radeon Vega|l=arch}} GPU operating at up to 1.3 GHz.
 +
 
 +
== Cache ==
 +
{{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}}
 +
{{cache size
 +
|l1 cache=384 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=4x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=2 MiB
 +
|l2 break=4x512 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=4 MiB
 +
|l3 break=1x4 MiB
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=GDDR5
 +
|frequency=1200 MHz
 +
|max mem=8 GiB
 +
|width=256 bit
 +
|max bandwidth=143.1 GiB/s
 +
}}
 +
 
 +
== Graphics ==
 +
The Z+ features a {{amd|vega|Radeon Vega|l=arch}} GPU with 24 compute units. The Compute Units operate at 1,300 MHz, each with 64 32-bit [[floating point]] [[multiply-accumulate]] units. At 1.3 GHz with 128 FLOP/cycle this chip can deliver 3.994 [[TFLOPS]] raw peak performance - about 66% the performance of the {{microsoft|Scorpio Engine}} (6 TFLOPS) and three times its predecessor.
 +
 
 +
<table class="wikitable">
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<tr><th colspan="2">Z+ GPU</th></tr>
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<tr><th>Unified shaders</th><td>1536 (64 × 24 CUs)</td></tr>
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<tr><th>[[raster operation units|ROPs]]</th><td>32</td></tr>
 +
<tr><th>[[texture mapping units |TMUs]]</th><td>96</td></tr>
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<tr><th>Peak Performance</th><td> ~4 TFLOPS (3,994,000,000,000 [[FLOPS]])</td></tr>
 +
</table>
 +
 
 +
{{integrated graphics
 +
| gpu                = Radeon Vega
 +
| device id          =
 +
| designer            = AMD
 +
| execution units    = 24
 +
| unified shaders    = 1536
 +
| max displays        = 3
 +
| max memory          = 8 GiB
 +
| frequency          =
 +
| max frequency      = 1,300 MHz
 +
 
 +
| output crt          =
 +
| output sdvo        =
 +
| output dsi          =
 +
| output edp          =
 +
| output dp          = Yes
 +
| output hdmi        = Yes
 +
| output vga          =
 +
| output dvi          =
 +
 
 +
| directx ver        = 12
 +
| vulkan ver        = 1.1
 +
| opengl ver        = 4.6
 +
| opencl ver        = 2.0
 +
| hdmi ver          =
 +
| dp ver            =
 +
| edp ver            =
 +
| max res hdmi      =
 +
| max res hdmi freq  =
 +
| max res dp        =
 +
| max res dp freq    =
 +
| max res edp        =
 +
| max res edp freq  =
 +
| max res vga        =
 +
| max res vga freq  =
 +
}}
 +
{{zen with vega hardware accelerated video table|col=1}}
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=Yes
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=No
 +
|avx512cd=No
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=No
 +
|avx512dq=No
 +
|avx512vl=No
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=Yes
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=Yes
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=No
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=No
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|dlboost=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=Yes
 +
|amdv=Yes
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=Yes
 +
|sensemi=Yes
 +
|xfr=Yes
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=Yes
 +
|amdpbod=No
 +
}}

Latest revision as of 13:48, 12 May 2019

Edit Values
FireFlight
General Info
DesignerAMD,
Zhongshan Subor
Model NumberFireFlight
MarketConsole, Desktop
IntroductionAugust 3, 2018 (announced)
August 3, 2018 (launched)
ShopAmazon
General Specs
Frequency3,000 MHz
Bus typePCIe 3.0
Bus rate4 × 8 GT/s
Clock multiplier30
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen
TechnologyCMOS
Word Size64 bit
Cores4
Threads8
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)

FireFlight is a semi-custom quad-core x86 SoC designed by AMD for Zhongshan Subor for their gaming PC/consoles and introduced in mid-2018. The Z+ features four Zen cores operating at 3 GHz along with a 24-CU Radeon Vega GPU operating at up to 1.3 GHz.

Cache[edit]

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$256 KiB
262,144 B
0.25 MiB
4x64 KiB4-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  4x512 KiB8-way set associativewrite-back
L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  1x4 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeGDDR5
Max Mem8 GiB
Frequency1200 MHz
Width256 bit
Max Bandwidth143.1 GiB/s
146,534.4 MiB/s
153.652 GB/s
153,652.455 MB/s
0.14 TiB/s
0.154 TB/s

Graphics[edit]

The Z+ features a Radeon Vega GPU with 24 compute units. The Compute Units operate at 1,300 MHz, each with 64 32-bit floating point multiply-accumulate units. At 1.3 GHz with 128 FLOP/cycle this chip can deliver 3.994 TFLOPS raw peak performance - about 66% the performance of the Scorpio Engine (6 TFLOPS) and three times its predecessor.

Z+ GPU
Unified shaders1536 (64 × 24 CUs)
ROPs32
TMUs96
Peak Performance ~4 TFLOPS (3,994,000,000,000 FLOPS)

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPURadeon Vega
DesignerAMD
Execution Units24Max Displays3
Unified Shaders1536
Max Memory8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
Burst Frequency1,300 MHz
1.3 GHz
1,300,000 KHz
OutputDP, HDMI
Standards
DirectX12
OpenGL4.6
OpenCL2.0
Vulkan1.1

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
FMA44-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SenseMISenseMI Technology
XFRExtended Frequency Range
Boost 2Precision Boost 2
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