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|designer=Zhaoxin
 
|designer=Zhaoxin
 
|manufacturer=HLMC
 
|manufacturer=HLMC
|manufacturer 2=SMIC
 
 
|introduction=December 28, 2017
 
|introduction=December 28, 2017
 
|process=28 nm
 
|process=28 nm
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|extension 14=TXT
 
|extension 14=TXT
 
|extension 15=RDSEED
 
|extension 15=RDSEED
|l1i=32 KiB
 
|l1i per=core
 
|l1i desc=8-way set associative
 
|l1d=32 KiB
 
|l1d per=core
 
|l1d desc=8-way set associative
 
|l2=4 MiB
 
|l2 per=cluster
 
|l2 desc=8-way set associative
 
 
|predecessor=Zhangjiang
 
|predecessor=Zhangjiang
 
|predecessor link=zhaoxin/microarchitectures/zhangjiang
 
|predecessor link=zhaoxin/microarchitectures/zhangjiang
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== Release Dates ==
 
== Release Dates ==
 
[[File:zhaoxin roadmap (2017).png|right|400px]]
 
[[File:zhaoxin roadmap (2017).png|right|400px]]
Development for WuDaoKou started in August 2013. The basic architecture design was completed by June 2014 with basic design done in July 2015. WuDaoKou hardware implementation was completed in April 2016 and [[taped out]] in August 2016. Final verification was done in October 2016 and mass production started in October 2017. The KX-5000 (formerly ZX-D) was announced at Semicon China 2017. The architecture and SKUs were officially unveiled at a conference on December 28, 2017.
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Development for WuDaoKou started in August 2013. The basic architecture design was completed by June 2014 with basic design done in July 2015. WuDaoKou hardware implementation was completed in April 2016 and [[taped out]] in August 2016. Final verification was done in October 2016 and mass production started in October 2017. The KX-5000 (formerly ZX-D) was announced at Semicon China 2017. The architecture and SKUs were officially unveiled at a conference on December 28, 2018.
  
 
[[File:wudaokou timeline.png|500px]]
 
[[File:wudaokou timeline.png|500px]]
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=== Block Diagram ===
 
=== Block Diagram ===
:[[File:wudaokou soc block diagram.svg|550px]]
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{{empty section}}
  
 
=== Memory Hierarchy ===
 
=== Memory Hierarchy ===
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*** Per core
 
*** Per core
 
** L2 Cache
 
** L2 Cache
*** 4/8 MiB, 16/32-way set associative
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*** 4 MiB, 32-way set associative
 
*** Per quad-core cluster
 
*** Per quad-core cluster
 
* System DRAM
 
* System DRAM
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== Overview ==
 
== Overview ==
[[File:wudaokou overview.svg|right|350px]]
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{{empty section}}
WuDaoKou is largely a brand new architecture designed by Zhaoxin. This is a departure from earlier microarchitectures such as {{\\|ZhangJiang}} which were a lightly modified version of [[VIA Technologies]] ([[Centaur Technology|Centaur]]) architecture. WuDaoKou is a new and complete [[SoC]] design. Whereas prior processors had separate [[dies]] connected together over the legacy [[front-side bus]], the new design is a single-die [[system-on-a-chip]] design that features [[8 cores|8]] integrated [[x86]] cores consisting of two clusters of four cores each connected over a new point-to-point crossbar, improving the internal bandwidth and latency considerably. The new chip also integrated the memory controller and the rest of the [[north-bridge]] on-die as well which further improved latency, bandwidth, and performance. The new chip also has an [[integrated graphics processor]] supporting 4K resolution and up to three screens via an array of display ports.
 
 
 
Overall, [[Zhaoxin]] has reported the new microarchitecture to have 25% improvement in [[IPC]], 140% improvement in multi-core workloads, and 120% higher memory access bandwidth.
 
 
 
=== Uncore ===
 
WuDaoKou features a new point-to-point high-speed interconnect [[crossbar]] which replaces the [[front-side bus]] from prior architectures. The new crossbar reduces the latency and provides facilities for control flow and cache coherency. Going through the crossbar is also the newly integrated graphics processor as well the memory controller. The new memory controller now supports up to dual-channel [[DDR4]] with data rates of up to 2400 MT/s (although current SKUs only seem to support up to 2133 MT/s). [[Zhaoxin]] has stated that this is the first domestic CPU to have a dual-channel DDR4 memory controller.
 
  
 
== Core ==
 
== Core ==
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== Die ==
 
== Die ==
 
[[File:wudaokou floorplan at conference.png|right|250px]]
 
[[File:wudaokou floorplan at conference.png|right|250px]]
 
=== Core module ===
 
: [[File:wudaokou core.png|500px]]
 
 
 
: [[File:wudaokou core (annotated).png|500px]]
 
 
=== Octa-core die ===
 
 
* [[HLMC]] [[28 nm process]]
 
* [[HLMC]] [[28 nm process]]
 
*  187 mm² die size
 
*  187 mm² die size
 
* 2,100,000,000 transistors
 
* 2,100,000,000 transistors
  
: [[File:wudaokou die shot.png|class=wikichip_ogimage|650px]]
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: [[File:wudaokou floorplan.png|600px]]
 
 
  
: [[File:wudaokou die shot (annotated).png|650px]]
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: [[File:wudaokou floorplan (annotated).png|600px]]
  
 
== All WuDaoKou Processors ==
 
== All WuDaoKou Processors ==
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</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}
 
== Documents ==
 
* [[:File:wudaokou.pdf|WuDaoKou]]
 
  
 
== References ==
 
== References ==
 
* Information was obtained directly from Zhaoxin
 
* Information was obtained directly from Zhaoxin
 
* [https://fuse.wikichip.org/news/733/zhaoxin-launches-their-highest-performance-chinese-x86-chips/ Zhaoxin launches their highest-performance Chinese x86 chips]
 
* [https://fuse.wikichip.org/news/733/zhaoxin-launches-their-highest-performance-chinese-x86-chips/ Zhaoxin launches their highest-performance Chinese x86 chips]

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codenameWuDaoKou +
core count2 +, 4 + and 8 +
designerZhaoxin +
first launchedDecember 28, 2017 +
full page namezhaoxin/microarchitectures/wudaokou +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerHLMC + and SMIC +
microarchitecture typeCPU +
nameWuDaoKou +
pipeline stages18 +
process28 nm (0.028 μm, 2.8e-5 mm) +